Fujitsu F2MC-8L F202RA Hardware Manual page 338

CHAPTER 14 8-BIT SERIAL I/O
Table 14.4-1 Explanation of Functions of Each Bit in Serial Mode Register (SMR) (2/2)
Bit name
BDS:
bit1 Transfer direction
selection bit
SST:
bit0
Serial I/O transfer start bit
322
This bit is used to select whether to transfer serial data, starting at the lowest
bit (LSB first, BDS = 0) or the highest bit (MSB first, BDS = 1). When this
bit is set to "0", serial data is transferred, starting at the lowest bit. When it is
set to "1", serial data is transferred, starting at the highest bit.
Note:
If this bit is rewritten after serial data has been written to the SDR to
replace higher data with lower data, the data in the SDR becomes invalid.
• This bit is used to control serial I/O transfer start and allowance. It can
also be used to judge whether serial I/O transfer terminated.
• If this bit is set to "1" when the internal shift clock is selected (when the
CKS1 and CKS0 bits are not 11
serial I/O transfer is started.
• If this bit is set to "1" when the external shift clock is selected (when the
CKS1 and CKS0 bits are 11
clock counter is cleared. The transfer side enters the external shift clock
input wait state.
• When serial I/O transfer terminates, this bit is set (cleared) to "0" and the
SIOF bit is set to "1".
• If this bit is set to "0" during serial I/O transfer (SST = 1), serial I/O
transfer is suspended.
When serial I/O transfer is suspended, it is necessary to reset the SDR of
the data output side and restart data input side transfer (clear the shift
clock counter).
Function
), the shift clock counter is cleared and
B
), serial I/O transfer is allowed and the shift
B