Acer 390 Series Service Manual page 73

Table 2-3 M1531 Signal Descriptions
Signal Type
DEVSELJ I/O
Group B
IRDYJ I/O
Group B
TRDYJ I/O
Group B
STOPJ I/O
Group B
LOCKJ I/O
Group B
REQJ[3:0] I
Group B
GNTJ[3:0] O
Group B
PHLDJ I
Group B
PHLDAJ O
Group B
PAR I/O
Group B
SERRJ/ I/O
CLKRUNJ Group B
Clock, Reset, and Suspend
HCLKIN I
Group A
RSTJ I
Group B
Clock, Reset, and Suspend
PCICLK I
Group B
PCIMRQJ O
Group B
SUSPENDJ I
Group C
OSC32KO I
Group C
Major Chips Description
Device Select. When the target device has decoded the address as its own
cycle, it will assert DEVSELJ.
Initiator Ready. This signal indicates the initiator is ready to complete the
current data phase of transaction.
Target Ready. This pin indicates the target is ready to complete the current
data phase of transaction.
Stop. This signal indicates the target is requesting the master to stop the
current transaction.
Lock Resource Signal. This pin indicates the PCI master or the bridge intends
to do exclusive transfers.
Bus Request signals of PCI Masters. When asserted, it means the PCI
Master is requesting the PCI bus ownership from the arbiter.
Grant signals to PCI Masters. When asserted by the arbiter, it means the PCI
master has been legally granted to own the PCI bus.
PCI bus Hold Request. This active low signal is a request from M1533/M1543
for the PCI bus.
PCI bus Hold Acknowledge. This active low signal grants PCI bus to
M1533/M1543.
Parity bit of PCI bus. It is the even parity bit across PAD[31:0] and CBEJ[3:0].
System Error or PCI Clock RUN. If the M1531 detects parity errors in
DRAMs, it will assert SERRJ to notify the system. As CLKRUNJ, this signal
will connect to M1533 CLKRUNJ to start, or maintain the PCI CLOCK. It is a
multifunction pin and determined by Index-77h bit0.
CPU bus Clock Input. This signal is used by all of the M1531 logic that is in
the Host clock domain.
System Reset. This pin, when asserted, resets the M1531 state machine, and
sets the register bits to their default values.
PCI bus Clock Input. This signal is used by all of the M1531 logic that is in
the PCI clock domain.
Total PCI Request. This signal is used to notify M1533/M1543 that there is
PCI master requesting PCI bus.
Suspend. When actively sampled, the M1531 will enter the I/O suspend
mode. This signal should be pulled high when the suspend feature is
disabled.
The refresh reference clock of frequency 32 KHz during suspend mode. This
signal should be pulled to a fixed value when the suspend feature is disabled.
Description
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