Acer 390 Series Service Manual page 67

2.2.1.1 Features
Supports all Intel/Cyrix/AMD/TI/IBM 586 processors. Host bus at 83.3, 75, 66, 60 and 50 MHz
at 3.3V/2.5V
Supports Linear Wrap mode for Cyrix M1 and M2
Write-Allocation feature for K6
Pseudo-Synchronous PCI bus access
(CPU bus: 75 MHz - PCI bus: 30 MHz, CPU bus: 83.3 MHz - PCI bus: 33 MHz)
Supports Pipelined-burst SRAM/Memory Cache
Direct mapped, 256 KB/512 KB/1 MB
Write-Back/Dynamic-Write-Back cache policy
Built-in 8K x 2 bit SRAM for MESI protocol to reduce cost and enhance performance
Cacheable memory up to 64 MB with 8-bit Tag SRAM
Cacheable memory up to 512 MB with 11-bit Tag SRAM
3-1-1-1-1-1-1-1 for Pipelined-burst SRAM/Memory Cache at back-to-back burst read and
write cycles
3.3V/5V SRAMs for Tag address
CPU single-read cycle L2 allocation
Supports FPM/EDO/SDRAM DRAMs
8 RAS lines up to 1 GB support
64-bit data path to memory
Symmetrical/Asymmetrical DRAMs
3.3V or 5V DRAMs
Duplicated MA[1:0] driving pins for burst access
No buffer needed for RASJ and CASJ and MA[1:0]
CBR and RAS-only refresh for FPM
CBR and RAS-only refresh and Extended refresh and self refresh for EDO
CBR and Self refresh for SDRAM
16 Qword deep merging buffer for 3-1-1-1-1-1-1-1 posted-write cycle to enhance high-
speed CPU burst access
6-3-3-3-3-3-3-3 for back-to-back FPM read page hit, 5-2-2-2-2-2-2-2 for back-to-back EDO
read page hit, 6-1-1-1-2-1-1-1 for back-to-back SDRAM read page hit, 2-2-2-2 for retired
data for posted write on FPM and EDO page-hit, x-1-1-1 for retired data for posted write
SDRAM page-hit
Enhanced DRAM page miss performance
Supports 64 Mbit (16M x 4, 8M x 8, 4M x 16) technology of DRAMs
Supports Programmable-strength RAS/CAS/ MWEJ/MA buffers
Supports Error Checking and Correction (ECC) and Parity for DRAM
Major Chips Description 2-21