Acer 390 Series Service Manual page 116

Table 2-8 65555 Pin Functions
Ball Pin Name
J18 MC0
J17 MC1
H19 MC2
G20 MC3
H18 MC4
G19 MC5
F20 MC6
G18 MC7
F19 MC8
D20 MC11
E19 MC12
F17 MC13
E18 MC14
D19 MC15
R20 MD0
P19 MD1
N18 MD2
P20 MD3
N19 MD4
M17 MD5
M18 MD6
N20 MD7
M19 MD8
M20 MD9
L18 MD10
L19 MD11(RMA16)
L20 MD12(rma17)
L17 MD13
K17 MD14
K20 MD15
C11 RAS0#
K18# PAS1#
C6 ROMOE#(MCLKOUT)
D11 ASAL#
A11 ASAH#
C16 CASBL#
B17 CASBH#
H20 ASCL#
J19 ASCH#
P18 ASDL#
R19 CASH#
B11 WEA#
A18 WEB#
J20 WEC#
T20 WED#
Note: All signals listed above are powered by MVCC and GND.
The 8 bytes comprising each 64-bit Qword are labeled AL, AH, BL, BH, CL, CH, DL, and DH.
There is a separate byte mask signal for each byte. Up to two banks can be supported, with
RAS0# controlling the first bank and RAS l# controlling the second bank. The address, data and
byte mask signals are the same for each bank.
2-70
Type Active
I/0 High DRAM data bits 32-47.
l/O High
l/O High
l/O High
l/O High
l/O High
l/O High
l/O High
l/O High
I/0 High
l/O High
l/O High
l/O High
l/O High
I/0 High DRAM data bits 48-63.
l/O High MD11-12 are also ROM addresses 16-17.
l/O High
l/O High MD11 and MD12, along with MB0 through MB15,
l/O High also serve as the address bus for the BIOS ROM
l/O High during startup (i.e., beore the system enables the
l/O High graphics controller memory interface).
l/O High
l/O High
I/0 High
l/O High
l/O High
l/O High
l/O High
l/O High
l/O High
Out Low RAS for DRAM Bank 0 (128K, 256K, or 512K by
Out Low 64-bit).
RAS for DRAM Bank 1.
Out Low Output Enable for BIOS ROM. May be
configured as MCLK output in test mode.
Out High CAS for dual-CAS EDO DRAM.
Out High
Out High Memory data byte mask signals. one mask
Out High signal for each of the eight data bytes in the 64-
Out High bit Qword. The masking is performed on a per-
Out High byte basis. A given byte is masked when the
Out High signal is high, or enabled when the signal is low.
Out High Masking is needed on write operations to specify
which bytes in the 64-bit word are being written.
Out Low MA[15:0] write enable for dual-CAS EDO DRAM
Out Low MB[15:0] write enable for dual-CAS EDO DRAM
Out Low MC[15:0] write enable for dual-CAS EDO DRAM
Out Low MD[15:0] write enable for dual-CAS EDO DRAM
Description
Service Guide