Acer 390 Series Service Manual page 53

Table 2-2 PCI1250 Terminal Functions
Name
PCI Interface Control Terminals
DEVSE V20
FRAME T19
GNT J20
GPIO2/LOCK V19
IDSEL N20
IRDY T18
PERR U18
REQ K17
SERR U19
Major Chips Description
No. I/O Type
I/O
I/O
I
I/O
I
I/O
I/O
O
O
Function
PCI device select. The PCI1250A asserts this signal
to claim a PCI cycle as the target device. As a PCI
initiator on the bus. the PCI1250A monitors this
signal until a target responds. If no target responds
before time-out occurs, then the PCI1250A will
terminate the cycle with an initiator abort.
PCI cycle frame. This signal is driven by the
initiator of a bus cycle. FRAME is asserted to
indicate that a bus transaction is beginning, and
data transfers continue while this signal is asserted.
When FRAME is deasseerted the PCI bus
transaction is in the final data phase.
PCI bus grant. This signal is driven by the PCI bus
arbiter to grant the PCI1250A access to the PCI bus
after current data transaction has completed. This
signal may or may not follow a PCI bus request
depending upon the PCI bus parking algorithm.
PCI bus general purpose l/O pins or PCI bus lock.
These pins are can be configured as PCI LOCK and
used to gain exclusive access downstream. Since
this functionality is not typically used, a general
purpose I/O may be accessed through this terminal.
This terminal defaults to a general purpose input,
and maybe configured through the GPIO2 Control
Register
Initalization device select. IDSEL selects the
PCI1250A during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI
address lines on the PCI bus.
PCI initiator ready. IRDY indicates the PCI bus
initiator's ability to complete the current data phase
of the transaction. A data phase is completed upon
a rising edge of PCLK where both IRDY and TRDY
are asserted. Until IRDY and TRDY are both
sampled asserted. wait states are inserted.
PCI parity error indicator. This signal is driven by a
PCI device to indicate that calculated parity does
not match PAR, when PERR is enabled through bit
6 of the command register.
PCI bus request. Asserted by the PCI1250A to
request access to the PCI bus as an initiator.
PCI system error. Output that is pulsed from the
PCI1250A, when enabled through the command
register, indicating a system error has occurred.
The PCI 1250A needs not be the target of the PCI
cycle in order to assert this signal. When SERR is
enabled in the control register, this signal will also
pulse indicating that address parity error has
occurred on a CardBus interface.
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