Acer 390 Series Service Manual page 59

Table 2-2 PCI1250 Terminal Functions
Name
CRSST W01
CCLKRUN U07
CardBus PC Card Address and Data Terminals (Slot A and Slot B)
CAD31 W08
CAD30 Y07
CAD29 W07
CAD28 V07
CAD27 Y06
CAD26 U05
CAD25 V04
CAD24 W04
CAD23 W03
CAD22 W02
C AD21 V03
CAD20 V02
CAD19 T04
CAD18 V01
CAD17 U02
CAD16 M04
CAD15 M02
CAD14 M03
CAD13 L04
CAD12 M01
CAD11 L03
CAD10 L02
CAD9 L01
CAD8 K03
CAD7 J01
CAD6 J04
CAD5 J03
CAD4 H02
CAD3 H01
CAD2 G01
CAD1 H03
CAD0 G02
Major Chips Description
No. I/O Type
C13 I/O
B09 O
B07 I/O
C08
B08
A08
D09
C11
B11
A12
C12
A13
B13
A14
C14
A15
B15
C18
C19
B20
E17
D18
C20
D19
E18
E19
G17
G18
F19
G19
F20
H18
G20
H19
Function
CardBus PC Card Reset. This signal is used to
bring CardBus PC Card specific registers,
sequencers, and signals to a known state. When
CRST is asserted, all CardBus PC Card signals
must be 3-statedt and the PCI1250A will drive
these signals to a valid logic level. Assertion may
be asynchronous to the CCLK. But deassertion
must be synchronous to the CCLK.
CardBus PC Card Clock Run. This signal is used
by a CardBus PC Card to request an increase in
the CCLK frequency. and the PCI 1 250A to
indicate that the CCLK frequency will be decreased.
PC Card Address and Data bus. These signals
make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address
phase of a CardBus cycle, CAD31:0 contain a 32-
bit address. During the data phase of a CardBus
cycle, CAD31:0 contain data. CAD31 is the most
significant bit
2-13