Acer 390 Series Service Manual page 60

Table 2-2 PCI1250 Terminal Functions
Name
CC/BE3 Y02
CC/BE2 T03
CC/BE1 N01
CC/BE0 K01
CPAR N03
Cardbus Interface Control Terminals
Slot A
CAUDIO Y05
CBLOCK P01
CCD1 G03
CCD2 W06
CDEVSEL R02
CFRAME U01
CGNT P03
2-14
No. I/O Type
B12 I/O
D14
B19
D20
A19 I/O
Slot B
D10 I
B18 I/O
H20 I
C09
A18 I/O
C15 I/O
D16 I
Function
CardBus Bus Commands and Byte Enables. The
command and byte enable signals are multiplexed
on the same CardBus terminals. During the
address phase of a CardBus cycle, CC/BE3:0
defines the bus command. During the data phase,
this four-bit bus is used as byte enables. The byte
enables determine which byte paths of the full 32-
bit data bus carry meaningful data. CC/BE0 applies
to byte 0 (CAD7:0), CC/BE1 applies to byte 1
(CAD15:8), CC/BE2 applies to byte 2 (CAD23:8),
and CC/BE3 applies to byte 4(CAD31:24)
CardBus Parity. In all CardBus read and write
cycles, the PCl1250A calculates even parity cross
the CAD and CC/BE buses. As an initiator during
CardBus cycles, the PC11250A outputs this parity
indicator with a one CCLK delay. As a target
during CardBus cycles, the calculated parity is
compared to the initiator's parity indicator; a
miscompare can result in a parity error assertion.
CardBus Audio. This signal is a digital input signal
from a PC Card to the system speaker. The
PCI1250A supports the binary audio mode, and
outputs a binary signal from the card to the
SPKROUT signal
CardBus Lock. This signal is used to gain exclusive
access to a target
CardBus Detect 1 and CardBus Detect 2. These
signals are used in conjunction with voltage sense
signals to identify ca d insertion and interrogate
cards to determine the operating voltage and card
type.
CardBus device select. The PCI1250A asserts this
signal to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the
PCI1250A monitors this signal until a target
responds. If no target responds before time-out
occurs, then the PCI1250A will terminate the cycle
with an initiator abort.
CardBus cycle frame. This signal is driven by the
initiator of a CardBus bus cycle. CFRAME is
asserted to indicate that a bus transaction is
beginning. and data transfers continue while this
signal is asserted. When CFRAME is deasserted
the CardBus bus transaction is in the final data
phase.
CardBus bus grant. This signal is driven by the
PCI1250A to grant a CardBus PC Card access to
the CardBus bus after ihe current data transaction
has completed.
Service Guide