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The transmitter FIFO cannot be written when this bit is cleared.
0 = Transmitter disabled
1 = Transmitter enabled
At reset, this bit is cleared to zero.
RxFL — Receiver FIFO Interrupt Trigger Level
These bits control the threshold at which a maskable interrupt is generated by the
receiver. A maskable interrupt is generated whenever the data level in the RX FIFO
reaches the selected threshold.
Value
00
01
10
11
At reset, these bits are cleared to zero.
RRDYEN — Receiver Ready Interrupt Enable
Setting this bit enables an interrupt when the receiver has data in the RX FIFO. The
fill level in the RX FIFO at which an interrupt is generated is controlled by the RxFL
bits. Clearing this bit disables RX interrupts.
0 = RX interrupt disabled
1 = RX interrupt enabled
At reset, this bit is cleared to zero.
RXEN — Receiver Enable
Setting this bit enables the receiver. If the RXD line is already low when the receiver is
enabled, the receiver does not recognize break characters, since it requires a valid
one-to-zero transition before it can accept any character.
0 = Receiver disabled
1 = Receiver enabled
At reset, this bit is cleared to zero.
IREN — Infrared Interface Enable
This active high bit enables the infrared interface.
0 = Infrared interface disabled
1 = Infrared interface enabled
At reset, this bit is cleared to zero.
RTSD EN — RTS Delta Interrupt Enable
This bit enables or disables RTS delta interrupts. The current status of the RTS pin is
read in the UART status register.
0 = RTS interrupt disabled
1 = RTS interrupt enabled
At reset, this bit is cleared to zero.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Table C-19 RxFL Field Settings
Interrupt if RX FIFO contains one or more character
Interrupt if RX FIFO contains four or more characters
Interrupt if RX FIFO contains eight or more characters
Interrupt if RX FIFO contains fourteen or more characters
PROGRAMMING REFERENCE
For More Information On This Product,
Go to: www.freescale.com
Meaning
MOTOROLA
C-39
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