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U0CR2 — UART0 Control Register 2
U1CR2 — UART1 Control Register 2
15
14
13
12
R
0
IRTS
CTSC
CTS
W
RESET:
0
0
0
IRTS — Ignore RTS
Setting this bit forces the RTS input signal presented to the transmitter to always be
asserted, effectively causing the external pin to be ignored. In this mode, the RTS pin
can be used as a general-purpose input.
0 = Transmit only while RTS pin is asserted
1 = Ignore RTS pin
At reset, this bit is cleared to zero.
CTSC — CTS Pin Control
This bit controls the operation of the CTS output pin. While this bit is set, the CTS out-
put pin is controlled by the receiver. When the RX FIFO has a pending overrun, the
CTS output is negated to indicate to the far-end transmitter to stop transmitting. While
the CTSC bit is negated, the CTS output pin is controlled by the CTS bit.
On reset, since this bit is cleared to zero, the CTS pin is controlled by the CTS bit,
which is also cleared to zero on reset. This means that on reset the CTS signal is
negated.
0 = CTS pin controlled by the CTS bit
1 = CTS pin controlled by the receiver
At reset, this bit is cleared to zero.
CTS — CTS bit
This bit controls the CTS pin while the CTSC bit is negated. While CTSC is asserted
this bit has no function.
0 = CTS pin is driven high (inactive)
1 = CTS pin is driven low (active)
At reset, this bit is cleared to zero.
PREN — Parity Enable
This bit enables or disables the parity generator in the transmitter and parity checker
in the receiver.
0 = Parity disabled
1 = Parity enabled
At reset, this bit is cleared to zero.
MOTOROLA
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11-12
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
11
10
9
8
0
0
0
PREN PROE STPB
0
Figure 11-5 UART Control Register 2
For More Information On This Product,
Go to: www.freescale.com
7
6
5
4
WS
0
0
0
0
10009082
1000A082
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
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