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interrupt will set the corresponding bit in EPFR. The outputs of this register drive the
corresponding input of the interrupt controller for those bits configured as edge
detecting. These bits are cleared by hardware reset.
C.8 ISPI Programming Model
These registers control the operation of the ISPI and report its status. The data regis-
ter exchanges data with external slave devices. After reset, all bits are cleared.
Access these registers with halfword accesses. Accesses other than halfword in size
result in undefined activity.
Table C-14 Interval Mode Serial Peripheral Interface Address Map
Address
10008000
10008002
10008004
10008006
10008008
to
10008FFF
C.8.1 ISPI Send/Receive Data Register
The ISPI send/receive data register (SPDR) contains data to be exchanged with
external devices. Either writing or reading this register clears any set interrupt.
SPDR — ISPI Data Register
15
14
13
12
R
W
RESET:
0
0
0
0
Rx DATA — Receive Data
This read-only register contains the data bits received from the shift register. Those
bits more significant than the size determined in CLOCK COUNT (ISPI control regis-
ter) return zeros when read. For example, if CLOCK COUNT = 0x8 (9-bit transfer),
then bits 15 to 9 are forced to zeros. The value in this register is updated at the end of
every transfer.
Tx DATA — Transmit Data
This write-only register contains the data bits to be transmitted to the external device.
Data is copied from this register to the shift register at the time that the XCH bit is set.
As data is shifted MSB first, outgoing data is MSB-justified relative to the CLOCK
COUNT field in the ISPI control register. For example, if the exchange length is ten
bits (CLOCK COUNT = 0x9), the MSB of the outgoing data is bit nine. The first bit
presented to the external device is bit nine, followed by the remaining nine less signif-
icant bits.
MOTOROLA
C-30
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
Use
ISPI Send/Receive Data Register (SPDR)
ISPI Control Register (SPCR)
ISPI Interval Control Register (SPICR)
ISPI Status Register (SPSR)
Reserved
11
10
9
8
Rx DATA
Tx DATA
0
0
0
0
Figure C-32 ISPI Data Register
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7
6
5
4
0
0
0
0
10008000
3
2
1
0
0
0
0
0
MMC2001
REFERENCE MANUAL
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