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NOTE
The juPD8251 can operate in either Asynchronous or Synchronous communication
modes. Understanding how the Mode Instruction controls the functional operation
of the USART is easiest when the device is considered to be two separate components,
one asynchronous and the other synchronous, which share the same support circuits
and package. Although the form at definition can be changed at w ill or "o n the fly ", the
two modes w ill be explained separately for clarity.
When a data characters w ritten into the juPD8251, the USART automatically adds
a START b it (low level or "space") and the number o f STOP bits (high level or
"m a rk") specified by the Mode Instruction. If Parity has been enabled, an odd or
even Parity bit is inserted just before the STOP bits(s), as specified by the Mode
Instruction. Then, depending on CTS and TxEN, the character may be transmitted
as a serial data stream at the TxD output. Data is shifted out by the falling edge of
TxC at TxC, TxC/16 or TxC/64, as defined by the Mode Instruction.
If no data characters have been loaded into the yPD8251, or if all available characters
have been transmitted, the TxD output remains "h ig h " (marking) in preparation
for sending the START b it o f the next character provided by the processor. TxD may be
forced to send a BREAK (continuously low) by setting the correct b it in the
Command Instruction.
The RxD input line is normally held "h ig h " (marking) by the transmitting device.
A falling edge at RxD signals the possible beginning of a START b it and a new
character. The START b it is checked by testing fo r a "lo w " at its nominal center
as specified by the BAUD RATE. If a "lo w " is detected again, it is considered valid,
and the b it assembling counter starts counting. The b it counter locates the approxi
mate center o f the data, parity (if specified), and STOP bits. The parity error flag (PE)
is set, if a parity error occurs. Input bits are sampled at the RxD pin w ith the rising
edge o f RxC. If a high is not detected for the STOP bit, which normally signals the end
of an input character, a framing error (FE) w ill be set. After a valid STOP bit, the input
character is loaded into the parallel Data Bus Buffer o f the /iPD8251 and the RxRDY
signal is raised to indicate to the processor that a character is ready to be fetched. If the
processor has failed to fetch the previous character, the new character replaces the old
and the overrun flag (OE) is set. All the error flags can be reset by setting a b it in the
Command Instruction. Error flag conditions w ill not stop subsequent USART operation.
North Star HSIO-4
C/D = 1
MODE INSTRUCTION
C/B = 1
SYNC CHARACTER 1
C/Ö = 1
SYNC CHARACTER 2
COMMAND INSTRUCTION
C/D = 1
>
C/D = 0
C/B = 1
COMMAND INSTRUCTION
C/D = 0
; J
C/D = 1
COMMAND INSTRUCTION
(T)
The second SYNC character is skipped if MODE instruction
has programmed the 8251 to single character Internal SYNC
Mode. Both SYNC characters are skipped if MODE instruction
has programmed the 8251 to ASYNC mode.
SYNC MODE
O N L Y ©
DATA
DATA
85
TYPICAL DATA BLOCK
MODE INSTRUCTION
DEFINITION
ASYNCHRONOUS
TRANSMISSION
ASYNCHRONOUS
RECEIVE
User/Techpical Manual
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