NorthStar HSIO-4 User's & Technical Manual page 86

PIN
SYMBOL
NO.
1,2. Data Bus Buffer
27, 28
5 - 8
26 V cc Supply Voltage
VCC
4 GND Ground
Read/Write Control Logic
Reset
21 RESET
Clock Pulse
20 CLK
WR
10 Write Data
13 RD Read Data
Control/Data
12 C/D
11 CS Chip Select
Modem Control
Data Set Ready
22 DSR
24 DTR Data Terminal Ready
RTS Request to Send
23
17 CTS Clear to Send
North Star HSIO-4
NAME
An 8-bit, 3-state bi-directional buffer used to
interface the 8251 to the processor data bus.
Data is transmitted or received by the buffer in
response to input/output or Read/Write instruc­
tions from the processor. The Data Bus Buffer
also transfers Control words. Command words,
and Status.
+5 volt supply
Ground
This logic block accepts inputs from the pro­
cessor Control Bus and generates control signals
for overall USART operation. The Mode
Instruction and Command Instruction registers
that store the control formats for device func­
tional definition are located in the Read/
Write Control Logic.
A "one" on this input forces the USART into the
"Idle" mode where it will remain until reinitial­
ized with a new set of control words. Minimum
RESET pulse width is t^y»
The CLK input provides for internal device tim ­
ing and is usually connected to the Phase 2 (TTL)
output of the pPB8224 Clock Generator.
External inputs and outputs are not referenced
to CLK, but the CLK frequency must be 30
times the Receiver or Transmitter clocks in the
synchronous mode and 4.5 times for the
asynchronous mode.
A "zero" on this input instructs the
to accept the data or control word which the
processor is writing out to the USART via the
data bus.
A "zero" on this input instructs the pPD8251
to place the data or status information onto the
Data Bus for the processor to read.
The Control/Data input, in conjunction with the
WR and RD inputs, informs USART to accept or
provide either a data character, control word or
status information via the Data Bus.
0 = Data; 1 = Control.
A "zero" on this input enables the USART for
reading and writing to the processor.
The pPD8251 has a set of control inputs and
outputs which may be used to simplify the
interface to a Modem.
The Data Set Ready input can be tested by the
processor via Status information. The DSR input
is normally used to test Modem Data Set Ready
condition.
The Data Terminal Ready output can be con­
trolled via the Command word. The DTR output
is normally used to drive Modem Data Terminal
Ready or Rate Select lines.
The Request to Send output can be controlled
via the Command word. The RTS output is
normally used to drive the Modem Request to
Send line.
A "zero" on the Clear to Send input enables the
USART to transmit serial data if the TxEN bit in
the Command Instruction register is enabled
(one).
FUNCTION
PD8251
m
81 User/Technical Manual
PIN IDENTIFICATION