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BUS PARAMETERS: ©
Ta * 0°C to 70*C; Vcc • 5.0V ; 5%. GN O - OV
Andress Stable before READ. <CS. C 0>
Andress «old Time ' o r READ. iCS. JD)
RE AO Pulse Width
Data Delay bom READ
READ to Data Floating
Recovery Time Between WRITES ©
Address Stable before WRITE
Address Hold Time fo r WRITE
WRITE Pulse Width
Data Set-Up Time f o r WRITE
Data Hold Time fo r WRITE
Clock Period ©
Clock Pulse Width
Clock Rise and F a l l Time
TxD Delay bom Fal l i n g Edge ol f *CT
Rx Data Set-Up Time t o Sampling Pulse
Rx Data Hold Time t o Sampling Pulse
Transmitter Input Clock Frequency
1 X 8aud Rate
16X and 64X Baud Rate
Transmitter Input Clock Pulse Width
1X Baud Rate
16X ano 64X Baud Rate
Transmitter Input Clock Pulse Delay
1 X Baud Rate
16X and 64X 8aud Rate
Receiver Input Clock Frequency
1X 8aud Rate
16X and 64X Baud Rate
Receiver Input Clock Pulse Width
1X Baud Rate
I6X and 64X Baud Rate
Receiver input Clock Pulse Delay
1X Baud Rate
I6X and 64X Baud Rate
TxRDY Delay bom Center ol Oato B i t
RxRDY Delay bom Center of Oata Bn
i n t e r nal Syndet Delay bom Center o f
Data Bn
External Syndet Set-Up Time before
F a l l i n g Eoge
* RxC
0
TxEMPTY Oelay bom Center ol Data Bn
Control Delay i>om Rising Edge o l
WRITE (TxE. DTR. RTSJ
Control to RE AO Set-Up T.me <DSR.
Notes:
©
AC timings measured a t V
q h
©
This recovery time i s lo r i n i t i a l i z a t i o n only, when MODE. SYNC1. SYNC2. C O M M A N O and f i r s t DATA BYTES a re written mto
the USART. Subsequent writing o f both C O M M A N D and DAT A are only allowed when TxRDY * 1 .
©
The TxC and RxC Ireauencies have the following limitations with respect t o CLK.
For IX Boud Rate, ifx or I
For 16X and 64X Baud Rate, »Tx o r lqx < 1/(4,5 t^yl
Figure 1.
North Star HSIO-4
LIMITS
MIN
TYP
RE AO
50
'AR
5
'RA
430
«RR
«RD
' OF
25
6
IRV
WRITE
20
1 AW
20
'WA
400
*WW
200
>DW
40
' WD
OTHER TIMING
.420
' CY
220
■ w .
0
«R.tF
*DT x
2
' SRx
2
'HRx
*Tx
DC
DC
' TPW
12
1
•TPD
15
3
*Rx
DC
DC
IRPW
12
1
*RPD
15
3
«Tx
' Rx
' I S
16
' ES
' TxE
' W C
' CR
16
4 2 . 0 . V
= 0.8, and with load c i r c u i t o l Fiqure 1 .
q l
„ * 1/(30
*
r
i c y
-100
Delay Versus A Capacitance (pF)
TEST LOAD CIRCUIT
79
TEST CONDITIONS
M A X
n s
ns
ns
ns
350
CL * lOOpF
200
ns
C L » lOOpF
CL - 15 pF
' CY
ns
ns
ns
ns
ns
1.35
l i t
ns
0.7tcY
50
ns
1
CL = lOOpF
PS
C L • lOOpF
C
• 100 pF
PS
l
56
KHz
520
KHz
' CY
■CY
' CY
' CY
56
KHz
520
KHz
' CY
' CY
16
CL 4 50 pF
' CY
20
' CY
25
•CY
16
•CY
16
CL • 50 oF
' CY
' CY
' CY
-5 0
0
+50
+100
A CAPACITANCE (pF)
Typical A Output
User/Technical Manual
AC CHARACTERISTICS
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