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8.2 BIO Unit EZU-EK25
8.2.1 BIO PCB
No.
Signal Name
1 SCK̲BIO̲N
2 SCK̲BIO̲P
3 S̲AD15〜1
4 S̲CBE<1..0>
5 S̲FRME*
6 S̲IRDY*
7 S̲TRDY*
8 S̲STOP*
9 S̲PRST*
10 SYNC1
11 SYNC2
12 64NS̲N
13 64NS̲P
14 FPGARESET*
15 BIOCONFDONE
16 R‑TRIG
17 BIO̲CS*
18 BIO̲Sdata
19 TMS̲COM
20 TDI̲COM
21 TCK̲BIO
22 TDO̲BIO
Terminal No.
IN/OUT
16E
IN
15E
IN
23C,24C,25C,26C,
IN/OUT
27C,28C,29C,30C,
31C,32C,33C,34C,
35C,36C,37C,38C
31A,33A
IN
29A
IN
27A
IN
25A
OUT
23A
OUT
35A
IN
20B
IN
20A
IN
16D
IN
15D
IN
26B
IN
4B
OUT
10B
OUT
7B
IN
4A
IN
17A
IN
15A
IN
17B
IN
15B
OUT
From/To
CNF4‑27
CNF4‑25
CNF3‑
37,39,41,43,45,47,
49,51,53,55,57,59,
61,63,65,67
CNF3‑33,35
CNF3‑27
CNF3‑25
CNF3‑23
CNF3‑21
CNF3‑29
CNF2‑17
CNF2‑15
CNF4‑21
CNF4‑23
CNF2‑73
CNF2‑25
CN80‑2,CNF2‑19
CNF2‑41
CNF2‑39
CNF3‑2
CNF3‑4
CNF3‑9
CNF3‑19
8 - 15
Description
Spci Clock
Spci Clock
Spci Address Data bus.
Byte Enable
Spci Cycle Frame
Spci Initiator Ready
Spci Target Ready
Spci Stop
Spci Reset
ECG SYNC1 signal
ECG SYNC2 signal
15.6MHz (64nS) System Clock.
15.6MHz (64nS) System Clock.
FPGA reset.
FPGA configuration begins after
FPGARESET* positive edge.
FPGA configuration
ECG R‑Wave Trig Signal
Time Stamp Chip Select
Time Stamp Serial Data
JTAG Test Mode Selector
JTAG Test Data input
JTAG Test Clock
JTAG Test Data output
L1E-EA0229
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