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No.
Signal Name
23
ADJ̲YSYNC*
24
DBF̲YSYNC*
25
YSYNC*
26
LCK
27
FFTSTART*
28
CNAD*
29
SYNCERR
30
SP̲SPEED<1..0>
31
SP̲USTRIG*
32
FPGARESET*
33
SYSRESET*
34
PWSW̲KB
35
STBY
36
STBY‑
36
TMS̲COM
37
TDI̲COM
38
TCK̲PRB
39
TCK̲CW
40
TCK̲DBF1
41
TCK̲DBF2
42
TCK̲BIO
43
TDO̲PRB
44
TDO̲CW
45
TDO̲DBF1
46
TDO̲DBF2
47
TDO̲BIO
48
S̲STOP*
49
S̲TRDY*
50
S̲IRDY*
51
S̲FRAME*
52
S̲PRST*
53
S̲PCLK
Terminal No.
IN/OUT
CNF2‑45
OUT
CNF2‑47
OUT
CNF2‑49
OUT
CNF2‑51
OUT
CNF2‑53
OUT
CNF2‑55
OUT
CNF2‑63
OUT
CNF2‑65,67
OUT
CNF2‑71
OUT
CNF2‑73
OUT
CNF2‑75
OUT
CNF2‑77
OUT
CNF2‑79
IN
CNF2‑80
IN
CNF3‑2
OUT
CNF3‑4
OUT
CNF3‑1
OUT
CNF3‑3
OUT
CNF3‑5
OUT
CNF3‑7
OUT
CNF3‑9
OUT
CNF3‑11
IN
CNF3‑13
IN
CNF3‑15
IN
CNF3‑17
IN
CNF3‑19
IN
CNF3‑21
IN
CNF3‑23
IN
CNF3‑25
OUT
CNF3‑27
OUT
CNF3‑29
OUT
CNF3‑31
OUT
From/To
DBF‑121E
DBF‑122E
NC
DBF‑122D
DBF‑137C
DBF‑137D
CN80‑3
CN8‑35,36
DBF‑118E
PRB‑17B,
DBF‑140C,
BIO‑26B,
CW‑100A
PRB‑18A,
DBF‑131A,
BIO‑23B,
CW‑100B,
CN80‑4
CN80‑7
CN51‑1,
JP10‑2
CN51‑2,
JP11‑2
PRB‑12E,
DBF‑140E,
CW‑103B,
BIO‑17A
PRB‑12D,
DBF‑139E,
CW‑102B,
BIO‑15A
PRB‑12C
CW‑105B
DBF‑140D
DBF‑139D
BIO‑17B
PRB‑12B
CW‑104B
DBF‑138E
DBF‑137E
BIO‑15B
DBF‑132D,
BIO‑23A
DBF‑132E,
BIO‑25A
DBF‑131D,
BIO‑27A
DBF‑131E,
BIO‑29A
DBF‑131B,
BIO‑35A
DBF‑131C,
BIO‑37A
8 - 11
Description
DBF̲Ysync Adjustment
DBF Ysync
Ysync
Latch Clock. US Beam parameters I
latched previous to Y‑SYNC*
assertion.
FFT Calculation Start Signal
CFM Calculation Start Signal
Sync Error Signal
Fujinon Probe Rotation Speed
Fujinon Scan Timing Signal
FPGA Reset.
FPGA Configuration begins after
FPGARESET* positive edge.
System Reset.
Asserted at Power On and Software
Boot.
Power Off Interruption to
EUB Software through KBIF.
Stand‑by Switch Signal.
Stand‑by Switch Signal.
JTAG TMS Signal
JTAG TDI Signal
PRB JTAG TCK Signal
CW JTAG TCK Signal
DBF JTAG TCK Signal
DBF JTAG TCK Signal
BIO JTAG TCK Signal
PRB JTAG TDO Signal
CW JTAG TDO Signal
DBF JTAG TDO Signal
DBF JTAG TDO Signal
BIO JTAG TDO Signal
S‑PCI Local Bus Control Signal
S‑PCI Local Bus Control Signal
S‑PCI Local Bus Control Signal
S‑PCI Local Bus Control Signal
S‑PCI Local Bus Control Signal
S‑PCI Local Bus
30.3ns(33MHz) Clock
L1E-EA0229
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