Table of Contents
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No.
Signal Name
6
DBF̲BEAM1*
7
DBF̲RSTART*
8
CWSYNC*
9
CK32ON
10 DBFCONFDONE
11 DMAFC<2..0>
12 ADJ̲YSYNC*
13 DBF̲YSYNC*
14 LCK
15 FFTSTART*
16 CAND*
17 SP̲USTRIG*
18 FPGARESET*
19 SYSRESET*
20 TMS̲COM
21 TDI̲COM
22 TCK̲DBF1
23 TCK̲DBF2
24 TDO̲DBF1
25 TDO̲DBF2
26 S̲STOP*
27 S̲TRDY*
28 S̲IRDY*
29 S̲ERAME*
30 S̲PRST*
31 S̲PCLK
32 S̲CBE<1..0>*
33 S̲AD<15..0>
34 CK4F0US̲P
35 CK4F0US̲N
36 S̲CLK̲DBF̲P
37 S̲CLK̲DBF̲N
38 CK32̲DBF̲P
39 CK32̲DBF̲N
40 CK64DBF̲P
41 CK64DBF̲N
42 DBF̲PRB̲D
43 PRB̲LCK
44 PRB̲DBF̲D
45 PRB̲CK
46 TRDIV̲N
Terminal No.
IN/OUT
113B
OUT
113C
OUT
112A
OUT
139C
OUT
138D
OUT
128D,129D,129E
IN
121E
IN
122E
IN
122D
IN
137C
IN
137D
IN
118E
IN
140C
IN
131A
IN
140E
IN
139E
IN
140D
IN
139D
IN
138E
OUT
137E
OUT
132D
OUT
132E
OUT
131D
IN
131E
IN
131B
IN
131C
IN
132B,132C
IN
132A,133A,134A,
IN/OUT CNF3‑
135A,133B,134B,
135B,133C,134C,
135C,133D,134D,
135D,133E,134E,
135E
126E
IN
127E
IN
146B
IN
146A
IN
124E
IN
125E
IN
125D
IN
126D
IN
113D
OUT
111D
OUT
114D
IN
112D
OUT
108E
OUT
From/To
CNF1‑97
CNF1‑99
CNF2‑21
CNF2‑23
CNF2‑27
CNF2‑33,35,37
CNF2‑45
CNF2‑47
CNF2‑51
CNF2‑53
CNF2‑55
CNF2‑71
CNF2‑73
CNF2‑75
CNF3‑2
CNF3‑4
CNF3‑5
CNF3‑7
CNF3‑15
CNF3‑17
CNF3‑21
CNF3‑23
CNF3‑25
CNF3‑27
CNF3‑29
CNF3‑31
CNF3‑33,35
37,39,41,43,45,
47,49,51,53,55,
57,59,61,63,65,
67
CNF4‑1
CNF4‑3
CNF4‑9
CNF4‑11
CNF4‑15
CNF4‑13
CNF4‑17
CNF4‑19
PRB‑13C
PRB‑14D
PRB‑13E
PRB‑13A
PRB‑15A
8 - 7
Description
Not used
Reception Start Signal
Not used
Not used
DBF FPGA config. Done signal
DMA function control number
DBF Ysync adjustment
DBF Ysync
Latch Clock. US Beam parameters
is latced previous to Y‑SYNC*
assertion.
FFT calculation start signal
CFM calculation start signal
Fujinon scan timing signal
FPGA reset
System reset
JTAG TMS signal
JTAG TDI signal
DBF JTAG TCK signal
DBF JTAG TCK signal
DBF JTAG TDO signal
DBF JTAG TDO signal
SPCI local bus control signal
SPCI local bus control signal
SPCI local bus control signal
SPCI local bus control signal
SPCI local bus control signal
SPCI local bus 30.3ns clock
SPCI local bus control signal
SPCI local bus data signal
Transmission 4 times Reference
Clock for DBF (Positive Pole)
Transmission 4 times Reference
Clock for DBF (Negative Pole)
SPCI clock for DBF
(positive edge)
SPCI clock for DBF
(negative edge)
DBF 32ns clock (positive edge)
DBF 32ns clock (negative edge)
DBF 64ns clock (positive edge)
DBF 64ns clock (negative edge)
DBF to PRBSW serial data
PRBSW I/O latch clock
PRBSW to DBF serial data
PRBSW I/O serial clock
Trans/Receive switch control
(LVDS Negative Pole).
L1E-EA0229
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