Uart Interface Design Guide - Huawei MU509 Hardware Migration Manual

HUAWEI 30 mm × 30 mm LGA Module
Hardware Migration Guide
Table 2-16 Differences of the UART interface
Pin Interface Name
No.
73 UART UART0_DSR
74 UART0_RTS
75 UART0_DCD
76 UART0_TX
77 UART0_RIN
G
78 UART0_RX
79 UART0_DTR
80 UART0_CTS
1 UART1_TX
2 UART1_RTS
3 UART1_CTS
4 UART1_RX
28 UART2_TX
29 UART2_RX

2.9.2 UART Interface Design Guide

Besides compatibility of the UART, designers must consider the time sequence of
signals. The UART signals externally connected with the LGA module must be
transmitted at least 3s after the LGA module is powered on. Otherwise, a sink current
occurs and the LGA module may be improperly powered on.
Issue 08 (2016-12-12)
MU509 MC509 MU609
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
CMOS 2.6 V CMOS 1.8 V
N N CMOS 1.8 V for
debugging
N N N
N N N
N N CMOS 1.8 V for
debugging
Reserved
Reserved
HUAWEI Proprietary and Confidential
Copyright © HUAWEI Technologies Co., Ltd.
LGA Interface Differences
MU709 ME209u-526
N
N
N
N
CMOS 1.8 V
N CMOS 1.8 V
N CMOS 1.8 V
CMOS 1.8 V
CMOS 1.8 V for debugging
CMOS 1.8 V for debugging
ME909u ME909s
CMOS 1.8
V
CMOS 1.8
V
CMOS 1.8
V
CMOS 1.8
V
CMOS 1.8
V
CMOS 1.8
V
N
N
N
N
42