Figure 2-1 Connections For The Pc Interrupt Logic Controller - GE VMIVME-7805 Hardware Reference Manual

Figure 2-1 Connections for the PC Interrupt Logic Controller

INT
Real-Tm
I/O Controller Hub
PMC
Site
INTR
CPU
Keybd Interrupt Com 2
Timer
8-15
IRQ0 IRQ1
IRQ2
Ethernet Ethernet Video,
Clock
Cltr/Sbus USB
Cltr
IRQ8 IRQ9
IRQ11
IRQ10
CONNECTIONS
MAPPED BY BIOS
ICH4-M
PCI INTERRUPT
PIRQA PIRQB PIRQC PIRQD
INTA
INTB
INTC
INTD
82540EM
Ethernet
The PCI-to-VME Bridge has the capability of generating an NMI via the PCI
SERR# line. Table 2-6 describes the register bits that are used by the NMI. The
SERR interrupt is routed through logic back to the NMI input line on the CPU.
The CPU reads the NMI Status Control register to determine the NMI source (bits
set to 1). After the NMI interrupt routine processes the interrupt, software clears
the NMI status bits by setting the corresponding enable/disable bit to 1. The NMI
Enable and Real-Time Clock register can mask the NMI signal and disable/enable
all NMI sources.
82540 MASTER-PORTS $020-$021
Unused Floppy
Com 1
Control
IRQ3 IRQ4 IRQ5 IRQ6
82540 SLAVE- PORTS $0A0-$0A1
Mouse Math AT Flash
Drive
Coproc Hard Drv
IRQ12 IRQ13 IRQ14 IRQ15
MAPPER
PIRQE
Timers/SRAM
FPGA
Unused
IRQ7
Universe IIB
PCI-to-VME
BRIDGE
Standard Features 33
V
M
E
Bus