Shield Analog I/O - Xilinx Arty A7 Reference Manual

22.8.2018
For more information on the electrical characteristics of the pins connected to the FPGA, please see the
(http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf)

11.2 Shield Analog I/O

The pins labeled A0-A11 and V_P/V_N are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the
inputs range from 0-1 V. On the pins labeled A0-A5 we use an external circuit to scale down the input voltage from 3.3V. This circuit is
shown in Figure 11.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to the
Arty A7's GND ()) that is applied to any of these pins. If you wish to use the pins labeled A0-A5 as Digital inputs or outputs, they are
also connected directly to the FPGA before the resistor divider circuit (also shown in Figure 11.2.1).
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty/arty_shield_analog_diff.png)
Figure 11.2.1 Arty A7 Single-Ended Analog Inputs
The pins labeled A6-A11 are connected directly to 3 pairs of analog capable pins on the FPGA via an anti-aliasing filter. This circuit is
shown in Figure 11.2.2. These pairs of pins can be used as differential analog inputs with a voltage difference between 0-1V. The even
numbers are connected to the positive pins of the pair and the odd numbers are connected to the negative pins (so A6 and A7 form an
analog input pair with A6 being positive and A7 being negative). Note that though the pads for the capacitor are present, they are not
loaded for these pins. Since the analog capable pins of the FPGA can also be used like normal digital FPGA pins, it is also possible to use
these pins for Digital I/O.
The pins labeled V_P and V_N are connected to the VP_0 and VN_0 dedicated analog inputs of the FPGA. This pair of pins can also be
used as a differential analog input with voltage between 0-1V, but they cannot be used as Digital I/O. The capacitor in the circuit shown
in Figure 11.2.2 for this pair of pins is loaded on the Arty.
(https://reference.digilentinc.com/_media/reference/programmable-logic/arty/arty_shield_analog_single.png)
Figure 11.2.2 Arty A7 Differential Analog Inputs
The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel
can be driven by any of the analog inputs connected to the shield pins. The XADC core is controlled and accessed from a user design via
the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA's
power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx
document titled 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter. A
demo that uses the XADC core is available on the Arty A7 Resource Center.
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