Consideration - Motorola DSP56009 User Manual

External Memory Interface
DRAM Refresh
The EMI physical address is generated using the LSBs of the calculated addresses to
represent row addresses, so running sequentially through the address space of a
large data buffer during a whole DRAM refresh cycle should cause a refresh of all of
the rows. The time to complete a refresh cycle can be halved by using two data
buffers such that their base addresses use different LSBs (row addresses) for half of
the required DRAM row addresses. The user must, however, run through both data
buffers sequentially at the same frequency.
Assume that:
• A 44.1 KHz audio sampling frequency is used and the main code loops once
every sample period.
• The external memory has 512 rows (256 K
of its rows every 8 ms.
• Two data-delay buffers are used and one access to each buffer is performed
in every sample period. The EMI increments the base address during each
access.
• The LSBs of the base addresses are chosen as follows:
– Buffer 1: EBAR (Most Significant Bits (MSBs)) arbitrary;
EBAR[8:0] = 000000000;
– Buffer 2: EBAR (MSBs) arbitrary; EBAR[8:0] = 100000000;
Running through 256 sequential locations in both data buffers assures that all the
rows are refreshed. The main code loops 352 times in 8 ms, accessing all DRAM
memory locations of the 9 LSBs of the physical address using the Incremented
Addressing mode. Since the LSBs of the physical addresses correspond to the row
addresses, all rows are refreshed. The same implementation can be extended using
4, 8, or 16 data-delay buffers.
4.4.2 DRAM Refresh OnCE
While the On-Chip Emulation (OnCE) port is in the Debug mode, regular operation
of the DSP core is suspended and no regular access to the DRAMs can occur. Stored
data can therefore be lost. In order to avoid such a situation the user should set the
ERED bit in the ERCR—see Section 4.2.8 EMI Refresh Control Register (ERCR).
Refresh cycles will then be initiated by the internal refresh timer according to the
ERCR setting.
4-32
Example 4-1 Refresh Cycle
™
Port Debug Mode Consideration
DSP56009 User's Manual
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4 or 8), and needs to refresh all
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