Spi Master Mode - Motorola DSP56009 User Manual

The SS line should be kept asserted during a data word transfer. If the SS line is
deasserted before the end of the data word transfer, the transfer is aborted and the
received data word is lost.
5.6.2

SPI Master Mode

The SPI Master mode is initiated by enabling the SHI (HEN = 1), selecting the SPI
2
mode (HI C = 0), and selecting the Master mode of operation (HMST = 1). Before
enabling the SHI as an SPI master device, the programmer should program the
proper clock rate, phase, and polarity in HCKR. When configured in the SPI Master
mode, the SHI external pins operate as follows:
• SCK/SCL is the SCK serial clock output.
• MISO/SDA is the MISO serial data input.
• MOSI/HA0 is the MOSI serial data output.
• SS/HA2 is the SS input. It should be kept deasserted (high) for proper
operation.
• HREQ is the Host Request input.
The external slave device can be selected either by using external logic or by
activating a GPIO pin connected to its SS pin. However, the SS input pin of the SPI
master device should be held deasserted (high) for proper operation. If the SPI
master device SS pin is asserted, the Host Bus Error status bit (HBER) is set. If the
HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service
the SHI Bus Error interrupt.
In the SPI Master mode the DSP must write to HTX to receive, transmit, or perform a
full-duplex data transfer. Actually, the interface performs simultaneous data receive
and transmit. The status bits of both receive and transmit paths are active; however,
the programmer may disable undesired interrupts and ignore non-relevant status
bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated, the
IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The
DSP programmer may write HTX (if the HTDE status bit is set) to initiate the transfer
of the next word. The HRX FIFO contains valid receive data, which may be read by
the DSP, if the HRNE status bit is set.
Note: Motorola recommends that an SHI individual reset (HEN cleared) be
generated before beginning data reception in order to reset the receive FIFO to
its initial (empty) state, such as when switching from transmit to receive data.
MOTOROLA DSP56009 User's Manual
Serial Host Interface
SHI Programming Considerations
5-25