Dram Relative Addressing - Motorola DSP56009 User Manual

Table 4-13 Word Address to Physical Address Mapping for SRAM
EAM SRAM EWL
[3:0] Max size [2:0]
4 × 32 K
0011 000
X01
X1X
4.3.3

DRAM Relative Addressing

The DRAM Relative Addressing modes (EAM[3:0] = 01xx) are used when
implementing data-delay buffers in DRAM. In DRAM relative addressing, each
word access is translated into physical addresses by first generating the row address
and then following with one or more column addresses. The row access is an
out-of-page (i.e., slow) access, while the subsequent column accesses are in-page
(i.e., fast) accesses. The row address is formed by taking part of the calculated word
address (the number of bits will be determined by the number of rows in the DRAM).
The column addresses are generated by taking the remaining bits of the word
address and appending from 0 to 3 extension bits to the right (forming the LSBs of
the column addresses). The extension bits are then used to generate the number of
column addresses required. Address pins that are not required are kept at the
MOTOROLA
EBW MCS0
0
MCS0 = MCS1 =
A0 & C0 A0 & C0
1
MCS0 = MCS1 =
A1 & C0 A1 & A0
0
MCS0 = MCS1 =
C0 & C1 C0 & C1
1
MCS0 = MCS1 =
A0 & C0 A0 & C0
0
MCS0 = MCS1 =
C1 & C2 C1 & C2
1
MCS0 = MCS1 =
C0 & C1 C0 & C1
DSP56009 User's Manual
External Memory Interface
MRAS MCAS
MCS2 =
A0 & C0
MCS2 =
A1 & A0
MCS2 =
C0 & C1
MCS2 =
A0 & C0
MCS2 =
C1 & C2
MCS2 =
C0 & C1
EMI Address Generation
(Continued)
MA15 MA [14:0]
A [15:1]
MCS3 =
A0 & C0
A [16:2]
MCS3 =
A1 & A0
A [14:0]
MCS3 =
C0 & C1
A [15:1]
MCS3 =
A0 & C0
A[13:0], C0
MCS3 =
C1 & C2
A [14:0]
MCS3 =
C0 & C1
4-27