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2.2
POWER
Power Name
V
PLL Power —V
CCP
(PLL). The voltage should be well-regulated and the input should be
provided with an extremely low impedance path to the V
V
Quiet Power—V
CCQ
logic. This input must be tied externally to all other chip power inputs.
The user must provide adequate external decoupling capacitors.
V
Address Bus Power —V
CCA
address bus I/O drivers. This input must be tied externally to all other
chip power inputs. The user must provide adequate external decoupling
capacitors.
V
Data Bus Power —V
CCD
bus I/O drivers. This input must be tied externally to all other chip
power inputs. The user must provide adequate external decoupling
capacitors.
V
Serial Interface Power —V
CCS
SAI. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
2.3
GROUND
Ground Name
GND
PLL Ground —GND
P
should be provided with an extremely low-impedance path to ground.
V
CCP
as possible to the chip package.
GND
Quiet Ground —GND
Q
processing logic. This connection must be tied externally to all other chip
ground connections. The user must provide adequate external
decoupling capacitors.
GND
Address Bus Ground —GND
A
the address bus I/O drivers. This connection must be tied externally to all
other chip ground connections. The user must provide adequate external
decoupling capacitors.
MOTOROLA
Table 2-2 Power Inputs
provides isolated power for the Phase Lock Loop
CCP
provides isolated power for the internal processing
CCQ
CCA
provides isolated power for sections of the data
CCD
Table 2-3 Grounds
is ground dedicated for PLL use. The connection
P
should be bypassed to GND
provides isolated ground for the internal
Q
DSP56009 User's Manual
Description
provides isolated power for sections of the
provides isolated power for the SHI and
CCS
Description
by a 0.47 µF capacitor located as close
P
provides isolated ground for sections of
A
Signal Descriptions
Power
power rail.
CC
2-5
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