Hardware Reset Operation - Motorola DSP56009 User Manual

3.8

HARDWARE RESET OPERATION

The processor enters the Reset processing state after the external RESET pin is
asserted (hardware reset occurs) for the specified minimum time (See DSP56009
Technical Data sheet). The Reset state:
• resets internal peripheral devices by initializing their control registers as
described in the individual peripheral sections,
• sets the modifier registers to $FFFF,
• clears the Interrupt Priority Register (IPR),
• clears the Stack Pointer (SP),
• clears the Scaling mode (S[1:0]), Trace mode (T), Loop Flag (LF), Double
precision Multiply mode (DM), and Condition Code Register (CCR) bits in the
Status Register (SR) and sets the Interrupt mask (I[1:0]) bits, and
• clears the Stop Delay (SD) bit and the Program RAM Enable (PEA and PEB)
bits in the OMR.
The DSP remains in the Reset state until the RESET pin is deasserted. When the
processor leaves the Reset state it:
• loads the chip operating mode (MC, MB, and MA) bits of the OMR from the
external mode select pins (MODC, MODB, MODA), and
• begins program execution of the bootstrap ROM starting at address $0000.
Note: Refer to the DSP56000 Family Manual for detailed information about the IPR,
SR, and OMR.
MOTOROLA
Memory, Operating Modes, and Interrupts
DSP56009 User's Manual
Hardware Reset Operation
3-19