Sharp ER-A57R1 Service Manual page 53

Pin No.
30 – 26 DO-D7 (Data Bus) – Input/output (3 state)
When the µPD8257 is programmed by the CPU (Z-80), the data bus accepts the upper/Lower byte of DMA address and
23 22, 21
TC register value output from the CPU, or 8-bit data to be loaded into the Mode Set register (Slave mode). When the
CPU wants to read the value of the DMA address register, TC register, or status register, the data bus is used to transfer
the pertinent data value to the CPU (Slave mode).
During the DMA cycle (when the µPD8257 is bus master), the data bus is used to transfer the upper byte of memory
address from a DMA address register to the µPD8212. This address byte is transferred at the beginning of a DMA cycle.
The data bus is subsequently used to transfer memory data in the remaining portion of the DMA cycle.
32 – 35 A0-A3 (Address Bus) – Input/output (3 state)
When in the Slave mode, these pins serve as inputs to select a register to be read or written. Hen in the Master mode,
these pins output the lower 4 bits of 16-bit memory address.
37 – 40 A4-A7 (Address Bus) – Output (3 state)
When in the Master mode, these pins output bits 4-7 of the 16-bit memory address. Hen in the Slave mode, these pins
are ser to high impedance.
36 TC (Terminal Count) – Output
The TC output Indicates to the currently selected I/O device that the current DMA cycle is the last cycle of the data block.
If the TC stop bit of the Mode Set register is set, the selected channel will be automatically disabled at the end of the
DMA cycle.
The TC signal is output when bit 14 of the TC register on the selected channel is reset to zero. The value (n-1) must be
loaded in the lower 14 bits of the TC register, where "n" is the number of DMA cycles to be executed.
5. Oscillator Circuit
The LSI system clocks and transfer clocks for the ER-52TR system
are obtained by dividing a single master clock. The master clock (16.0
MHz) is applied to the CLK pin (pin 1) of the MB62H149, where it is
divided into system clocks for the individual LSI chips. The resulting
clocks of φ(4MHz) and TXC (1 or 0.5 MHz) appear at pins 8 and 71,,
respectively.
CLK
MB62H149
TXC
Φ
6. Serial/Parallel Conversion for Data
Transmission
1) General
Since a serial synchronous transmission scheme is used for SRN
communications, serial/parallel conversion is equired on the sen
d/receive data. The serial/parallel converter circuit uses an MC68B54
Advanced Data Link Controller (ADLC). The ADLC converts D0-D7
parallel data into serial data in synchronicity with the TXC signal (pin
5), and converts serial data (RXD) into parallel in synchronicity with
the RXC signal (pin 4).
EID2
16.0 [MHz]
01
X1
To ADLC (1 or 0.48 [MHz})
System CLK (4 [MHz])
Fig. 25
Signal name/in-out/Description
4 ™ 10