Sharp ER-A57R1 Service Manual page 48

5
WRS (Write from sub), Input
Pin 6
Data write signal received from the subsystem (Z-80A) which is
used to create I/O and memory data write control signal.
6
MRD (Memory read), Output
Pin 11
Memory data read control signal sent to the subsystem
(memory) which is created with MREQ and RDS.
7
MWRO (Memory write), Output
Pin 24
Memory data write control signal sent to the subsystem
(memory) which is created with MREQ and RDS.
8
IO/WR (I/O write), Input/Output (3-state)
Pin 36
I/O data write control signal sent to the subsystem (peripheral
I/O) which is created with IORQ And WRS.
During the DMA mode, it is received from the DMAC to create
the memory to I/O data transfer control signal.
9
IO/RD (I/O read), Input/Output (3-state)
Pin 37
I/O data read control signal sent to the subsysystem (peripheral
I/O) which is created with IORQ and WRS. During the DMA
mode, it is received from the DMAC to create the I/O to memory
data transfer control signal.
Φ
AO, A1, A4, A5 (Address bus from sub CPU), In
Pin 21, 20, 19, 18
An input signal used to create the selection signal which the sub
reads the hardware flag and subsystem (peripheral I/O) 8-bit
data through the data bus.
Γ
A8, A9, A10, A15 (Address bus for DMA), Output (3-state)
Pin 17, 16, 15, 14
Used to create the memory address information on the basis of
the information from the DMAC during the DMA cycle. The
output has 3-stats and retains a high impedance except during
the DMA cycle.
Η
AEN (Address enable from DMAC), In
Pin 38
An input from the DMAC which is used to enable the DMAC to
control by isolating the system address bus from the CPU
(Z-80A) during the DMA cycle.
That is, A8, A9, A10, and A15 are set to output condition from
their high impedance state.
Ι
AST (Address strobe from DMAC), In
Pin 39
An input from the DMAC which is used to latch the information
from the DMAC Sent on the data bus with AST In the DMAC
cycle to create A8, A9, A10, and A15 address information.
ϑ
DAK01 (DMA acknowledge 0+1), Input
Pin 22
The subsystem uses four DMA channels; one each for
transmitting and receiving of data (DAK0, DAK1), and for read
and write of received data (DAK2, DAK3), DAK01 is a logical OR
of DAK0 with DAK1 which is used for DMA control of
transmission data.
Κ
DAK23 (DMA acknowledge 2+3), Input
Pin 41
This signal is a logical OR of DAK2 and DAK3 and is used for
DMA control of transmission data.
Λ
DRQRS (DMA request read to sub CPU), Output
Pin 42
An active low DMA request to the sub CPU to read data which is
normally connected to the DMA controller of the sub.
Μ
DRQWS A request to write to sub CPU), Outut
Pin 43
An active low DMA request to the sub CPU to write data which is
normally connected to the DMA controller of the sub CPU.
Ν
TCS (Terminal count from sub), Input
Pin 40
An active high signal which the subsystem uses to inform that
the current DMA cycle is the final cycle.
Ο
INTS (Interrupt to sub), Input
Pin 17
An interrupt which the controller uses to inform the sub that it
has data to be read or written. This output is a half duty
oscillation signal when active.
Π
WAIT (Wait signal), Output
Pin 13
This signal is used to provide synchronization for the DMAC and
the sub CPU with the link controller (ADLC) when transferring
data with the link controller (ADLC), that is, to wrtie a command
to the ADLC, to read status, and to write or read transmit or
receive data. This line is normally an input to the DMAC and sub
CPU WAIT (ready) line.
Θ
CLK (Clock input), Input
Pin 1
Basic frequency input which is used to derive system clock,
transmit/receive clock, and internal sync clock, [16MHz]
Ρ φ (clock out), Output
Pin 8
A system clock output which the basic oscillation is divided by
four, Since the basic frequency is normally at 16MHz, the
system clock output is a 4MHz.
Σ
TXC (Transmit clock), Output (for SRN)
Pin 71
As the basic frequency is divided 1/16 or 1/32, it is supplied as
the transmit clock for the SRN system.
Choice of 1/16 and 1/32 is dependent on the sub CPU.
Τ
TXD (Transmit data from ADLC), Input (for SRN)
Pin 72
Transmit data from the link controller (ADLC).
Υ
TDI (Transmit data to driver), Output (for SRN)
Pin 67
Transmit data which TXD is phase encoded with the transmit
clock which is an input to the line driver of the SRN.
ς
RDI (Receiver data from receiver), Input (for SRN)
Pin 66
Phase encoded data from the other end via the line receiver of
the SRN.
Ω
RXD (Receive data to ADLC), Input (for SRN)
Pin 70
Receive data (RXD) output as the phase encoded data from the
other end received via the receiver are demodulated within the
controller to separate it into the receive data (RXD) and receive
clock, which is normally an input to the link controller (ADLC).
Ξ
RXC (Receive clock to ADLC), Output (for SRN)
Pin 69
An output of the receive clock (RXC) which is normally supplied
to the link controller (ADLC).
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