Sharp ER-A57R1 Service Manual page 51

2) Actual DMAC Operations
Address bus
Data bus
CP U
(Z-80)
4
BUSRQ
2
BUSAK
DMA C
3
(8257)
Transfer from memory to I/O device
1 When the CPU wants to start a DMA cycle, it sets the number of
bytes to be transferred and the first address of the tansfer memory
area into the registers within the DMAC. The applicable I/O device
issues a DMA Request (DRQ) to the DMAC.
2 Receving the DRQ signal, the DMAC issues a BUSRQ (Bus Re-
quest) to the CPU to request for bus access control.
3 Upon receipt of the BUSRQ, the CPU floats both data and ad-
dress buses and returns a BUSAK to the DMA as soon as it
completes the current instruction execution cycle.
Bus access control is now passed to the DMAC.
4 The DMAC creates as memory Chip Select signal from the ad-
dress bus, and outputs the transfer data address and RD signal to
place the transfer data onto the data bus. At this point the DMAC
issues a DAK (DMA Acknowledge) to the I/O device to let to the
I/O device read the memory data on the data bus. The above
sequence is repeated until a single DMA cycle is completed.
* On this board, DMA transfer is performed between the ADLC and
memory, and between memory and MB62H149.
The DAK01 (pin 37) and DAK23 (pin 41) of the MB62H149 are the
results of the logical OR of DAK0 with DAK1 and DAK2 with DAK3
of the DMAC, respectively. The DMAC's DAK is controlled by the
MB62H149.
DMAC
25
DAK0
24
DAK1
14
DAK2
15
DAK3
8257
DAK01 is used for the DMA cycle for data transfer, while DAK23 is
used for data transfer with the host processor.
Memory
I/O device
4
DAK
DRQ 1
Fig. 23
MB62H149
22
DAK01
41
DAK23
Fig. 24
External
device
4 ™ 8