Sharp ER-A57R1 Service Manual page 52

3) DMAC (8257-2) Pin Functions
Pin No.
1 I/OR (I/O Read) – Active Low Input/output (3 state)
This pin functions as an input when is Slave mode. Application of a Low level to this pin reads the 8-bit status register
value or the upper/lower byte of the 16-bit DMA address register or 16-bit TC regsiter. When in the Master mode this pin
serves as a control output, which allows the device to receive data from an I/O device during the DMA write cycle.
2 I/OW (I/O Write) – Active Low input/output (3 state)
This pin function as an input when in Slave mode. Application of a Low level to this pin enables the data to be loaded
into the 8-bit mode set register or the upper/lower byte of the 16-bit DMA address register or TC register. When in the
Master mode this pin serves as a control output, which allows the device to write data into an I/O device.
3 MEMR (Memory Read) – Active Low output (3 state)
This pin is used to enable to be read from the addressed memory location during DMA read cycle. It is set to a high
impedance when in the Slave mode.
4 MEMW (Memory Write) – Active Low output (3 state)
This pin is used to enable data to be writen in to the addressed memory location during DMA write cycle. It is set to high
impedance when in the Slave mode.
5 MARK (Mark) – Output
This pin is used to indicate to the selected I/O device that the current DMA cycle is the 128th cycle as counted from the
preceding MARK.
A MARK always occurs at every 128 cycles as counted from the end of a data block. It occurs at every 128 cycle as
counted from the beginning of a data block only if the total number (n) of DMA cycles is an integral multiple of 128 (and
the value (n-1) is loaded in the TC register).
6 READY (Ready) – Input
If the low-speed memory used requires an extended memory cycle, appliyng an asynchronous Low level signal to this
pin causes the DMAC to place wait cycles on its internal state to extend the memory read/write cycle.
7 HLDA (Hold Acknowledge) – Input
This pin accepts an BUSAK signal returned from the CPU (Z-80) when the CPU acknowledges a hold request. The
signal indicates that the DMAC (µPD8257) has acquired bus access control. Once this signal is returned, the bus
outputs of the CPU are set to high impedance.
8 ADDSTB (Address Strobe) – Output
This pin is normally connected to the STB Input of the µPD8212 as a strobe, which is used to write the upper byte of
memory address from the data bus into the µPD8212 .
9 AEN (Address Enable) – Output
This pin is used to set the address and control bus outputs of the Z-80 CPU to high impedance if needed. It may also be
used to disable the system address bus by using the enable input of the address bus driver within the system. This is to
disable any response from non-DMA devices during the DMA cycle.
It may also be used to disconnect the µPD8257's data bus from the system data bus, so that no special timing restriction
be required for the sytem bus when the µPD8257 wants to transfer the upper byte of DMA address through its data bus.
When the µPD8257 is used for I/O device configuration (in contrast to memory map configuration), this AEN output is
disabled so that an I/O device is not selected when a DMA address is pleaced on the address bus. An I/O device must
be selected bye the DMA acknowledge output to the four channels.
10 HRQ (Hold Request) – Output
This pin is used to request system bus access control. It is connected to the BUSRQ input of the Z-80 when only one
chip of µPD8257 is used in the system. When two or more chips are used, an additional priority encoder is required to
assign priority to the multiple HRQ signal lines.
11 CS (Chip Select) – Active Low input
When in the Slave mode, this pin enables the I/O Read or I/O Write input of the µPD8257 when the device is to be read
or written, respectively. When in the Master mode, the CS is automatically disabled to prevent the device itself from
being selected during DMA operation.
12 CLK (Clock) – Input
Clock in (4MHz)
13 RESET (Reset) – Input
This pin normally accepts an asynchronous Reset output from the CPU. The Reset signal resets all control signals and
places the device into the Slave mode. Once a Reset signal is received, the µPD8257 aborts its current operation
regardless of the device status and enters the Idle set (SI).
25, 24, 14, 15 DACK0-DACK3 (DMA Acknowledge) – Active Low output
These pins indicate to the I/O devices attached to the respective channels that the DMA cycle has been acknowledged.
19 – 16 DRQ0-DRQ3 (DMA Request) – Input
These Pins are independent, asynchronous DMA request channels used for I/O devices to request DMA cycle to the
µPD8257. DRQ3 has the lowest priority, while DRQ0 has the highest, as long as the Rotary Priority mode is not
selected. DRQn input is kept high until a DACKn is received. During the Multi DMA Cycle mode (Burst mode), DRQn is
kept high until the DACKn for the last cycle is received.
Signal name/in-out/Description
4 ™ 9