Iv. Hardware Description For Er-A6In And Er-A5Rs - Sharp ER-A57R1 Service Manual

IV. HARDWARE DESCRIPTION FOR ER-A6IN
AND ER-A5RS
CHAPTER1. ER-A6IN
1. Block Diagram
CPU: Z80
HOST SYSTEM
BUS
D B
DMA
DATA BUS
CONTROLLER
OPC1
CONT
CONTROL BUS
BUS BUFFER
TRANSMISSION
LINK
CONTROLLER
Fig. 1 SRN controller board block diagram
Fig. 1 shows the block diagram of the controller board of the SHARP
RETAIL NETWORK. The Controller is connected to the system bus of
the host system as one of I/O. Inside of the controller consists of Z-80
CPU, transmission link controller, DMA control circuit, ROM, RAM,
modulator, demodulator, carrier detection circuit, collision detect
circuit and so on.
Data communications with the host system is performed by the
handshaking by byte. The controller side functions with DMA (Direct
Memory Access) and is capable of data transmission without waiting
for the host system side.
∗ OPC1 is used only as a bus buffer. (In order to provide compatibil-
ity between the host CPU in the ECR side and H8/510.)
2. CPU Description (Z-80)
For details on the CPU, see the Cash Register Basic Manual.
Pin Connections (C-MOS Version used)
Input/
Pin Signal name
Output
1 A11 Out
2 A12 Out
3 A13 Out
4 A14 Out
5 A15 Out
φ
6 In
7 D4 I/O
8 D3 I/O
9 D5 I/O
10 D6 I/O
ROM CLOCK
CIRCUIT
COLLISION
DETECTION
RAM
CARRIER
DETECTION
MODULATOR
DEMODU-
LATOR
Description
Address Bus A11
Address Bus A12
Address Bus A13
Address Bus A14
Address Bus A15
CLK4 (MHz)
Data Bus D4
Data Bus D3
Data Bus D5
Data Bus D6
Pin Signal name
11 VCC
12 D2
13 D7
14 D0
15 D1
16 INT
17 NMI
18 HALT
19
MREQ
20 IOREQ
21 RD
22 WR
23 BUSAK
24 WAIT
25 BUSRQ
26 RES
EXTERNAL
CABLE
27 M1
28 RFSH
29 GND
30 A0
31 A1
32 A2
33 A3
34 A4
35 A5
36 A6
37 A7
38 A8
39 A9
40 A10
3. Description of MB62H149
1) Outline
The MB62H149 is a semi-custom LSI chip for the peripheral circuits
in the SRN (SHARP Retail Network), its main function is to
communicate data with the host CPU and control the peripheral
circuits and transmission control circuits of the Sub CPU (Z-80). Fig.
2. shows the general configuration of the functions:
HOST CPU
4 ™ 1
Input/
Output
— +5V
I/O Data Bus D2
I/O Data Bus D7
I/O Data Bus D0
I/O Data Bus D1
In Interrupt
In Non Maskable Interrupt
Out HALT
Out Memory Request
Out I/O Request
Out Read
Out Write
Out Bus acknowledge
In WAIT
In Bus Request
In Reset
Out M1 cycle
Out Refresh
— GND
Out Address Bus A0
Out Address Bus A1
Out Address Bus A2
Out Address Bus A3
Out Address Bus A4
Out Address Bus A5
Out Address Bus A6
Out Address Bus A7
Out Address Bus A8
Out Address Bus A9
Out Address Bus A10
SUB-CPU TIMER
DMAC
(Z-80)
COUNTER
DATA HAND
PERIPHERAL
SHAKING
CIRCUIT
CIRCUIT
Fig. 2
Description
Line
ADLC
TRANS-
MISSION
CONTROL
CIRCUIT
MB62H149