Sharp ER-A57R1 Service Manual page 49

Ψ
RTS (Request to send), Input (for SRN)
Pin 68
An input from the link controller (ADLC) which becomes active
low during transmission. The controller uses it for controlling the
collision detect circuit and modem circuit.
Ζ
LCS (Link controller chip select), Output
Pin 76
A chip select signal for the link controller (ADLC) in which the
sub CPU synchronizes with the DMCA.
[
IRQ (Interrupt request from ADLC), Input
Pin 75
An Interrupt request from the link controller (ADLC).
∴
E (Enable clock to ADLC), Input
Pin 74
Link controller (ADLC) enable clock which the sub CPU
synchronizes with the DMAC for data read to write.
]
RS0 (Register select 0), Outpt
Pin 79
Command and status register select signal for the link controller
(ADLC).
⊥
RS1 (Register select 1), Output
Pin 78
Command and status register select for the link controller
(ADLC) which is used in conjunction with RS0 above.
_
MSK (Mask signal), Output
Pin 80
Used to mask the signal to avoid DMA looping, except for other
than the data transmit/receive DMA request signal (input from
the link controller (ADLC), normally).

COL (Collision detect signal), Input
Pin 65
To avoid collision on the line, the data sent, from this side are
compared with the data on the line. In other words, when the
data sent are equal to the on line, no collision is assumed
existing. If not equal, an occurrence of data collision is assumed.
This line is, therefore, the input of the data sent from this side.
α
TM0 (Timer 0), Input
Pin 9
A clock of a given interval (100 msec) sent from the subsystem's
timer and counter. It is used to create the carrier off wait signal
and back-off timer within the controller.
β
TM1 (Timer 1), Output
Pin 10
Back-off timer output is a clock pulse ten times the TM0
frequency (T1=10xT0), where T1 is TM 1 clock and T0 is a TM0
clock.
•
Sub CPU read timing chart
A0, A1, A4, A5
IORQ
TAI
RDS
D0-D7
TIA
TRWK
TRDG TRDH
Fig. 10
•
Sub CPU write timing
A0, A1, A4, A5
IORQ
WRS
D0-D7
•
Sub DMA memory write timing
Φ
T AE L
AEN
TSTL
AST
T A K
DAK01
DAK23
T DC L
IO/RD
TWAG
WAIT
LCS
MWR
TE OG TEOH
E
•
MRD timing
MREQ
RDS
MRD
•
MWR timing
MREQ
WRS
MWR
4 ™ 6
TAI
TWWK
TDWK
Fig. 11
T D Q
T ST T
T A K
TD CT
T WA H
T LC G T LC H
TMWG T MW H
Fig. 12
TMRG
Fig. 13
TMWG
Fig. 14
TIA
TWDK
* LCSO remain high level
for DK2, 3
TMRH
TMWH