I/O & Memory Map - Motorola DSP96002 User Manual

3. If the core is doing one external access and the DMA is also doing an external access
thorough the other port, and the core access is delayed, the access by the DMA in the
other port is also delayed. This happens because the chip clock generates wait states and
the whole chip stops. Also, the arbitration between DMA and core cannot continue if the
core is frozen.
4. If one of the DMA channels is accessing external memory thorough a port, and the access
is delayed due to bus arbitration or memory wait, the second DMA channel will also stop,
since the DMA mechanism does not distinguish between the two channels.
5. If the Data ALU is executing a floating point instruction that requires normalization cycles
(IEEE mode with denormalized numbers), the Data ALU may freeze the clock for the other
chip sections including the DMA. In this case, the DMA operation will be slowed down.
7.6 I/O MEMORY MAP
Internal I/O peripherals occupy the top 128 locations in X memory space. External I/O peripherals occupy
the top 128 locations in Y memory space. Figure 7-27 shows the I/O memory map for the internal I/O pe-
ripherals.
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