Instruction Format - Motorola DSP96002 User Manual

Bcc
BRA
BRCLR
BRSET
BScc
BSCLR
BSR
BSSET
DEBUG
FBcc
FBScc
FFcc
FFcc.U
FJcc
FJScc
FTRAPcc
IFcc
IFcc.U
ILLEGAL
Jcc
JCLR
JMP
JScc
JSCLR
JSET
JSR
JSSET
NOP
RESET
RTI
RTR
RTS
STOP
TRAPcc
WAIT
6.3

INSTRUCTION FORMAT

Because of the multiple bus structure and the parallelism of the DSP96002, up to 3 data transfers may be
specified in the instruction word - one on the X Data Bus, one on the Y Data Bus and one within the Data
ALU. A fourth data transfer is generally implied and occurs in the Program Controller (instruction word
fetch, program looping control, etc.). Each data transfer will involve a source and a destination.
6 - 6
Branch Conditionally
Branch Always
Branch if Bit Clear
Branch if Bit Set
Branch to Subroutine Conditionally
Branch to Subroutine if Bit Clear
Branch to Subroutine
Branch to Subroutine if Bit Set
Enter Debug Mode
Branch Conditionally
Branch to Subroutine Conditionally (Floating-Point Condition)
Conditional Data ALU Operation without CCR Update
Conditional Data ALU Operation with CCR Update
Jump Conditionally
Jump to Subroutine Conditionally
Conditional Software Interrupt
Conditional Data ALU Operation without CCR Update
Conditional Data ALU Operation with CCR Update
Illegal Instruction Interrupt
Jump Conditionally
Jump if Bit Clear
Jump
Jump to Subroutine Conditionally
Jump to Subroutine if Bit Clear
Jump if Bit Set
Jump to Subroutine
Jump to Subroutine if Bit Set
No Operation
Reset Peripheral Devices
Return from Interrupt
Return from Subroutine and Restore Status Register
Return from Subroutine
Stop Processing (low power stand-by)
Conditional Software Interrupt
Wait for Interrupt (low power stand-by)
Figure 6-7. Program Control Instructions
DSP96002 USER'S MANUAL MOTOROLA