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The minimal memory read procedure is 6 program words and 16 clock cycles. The first move triggers the X
Memory Read interrupt request in the slave. The interrupt service routine in the slave takes 8-12 clock cy-
cles to execute. If there are other interrupts with higher priority the response to this interrupt may be delayed.
Only then can the master continue with the second move to read the data.
7.4.21.11
DSP96002 to DSP96002 Transfers Using On-Chip DMA Controllers
Data transfers done by the on-chip DMA Controllers do not require intervention by the core. Since the DMA
has dedicated internal data paths and internal memory slots, no penalty is imposed on execution time of the
core processing. However, there is overhead associated with the initialization procedure for the on-chip
DMA channels. The following initialization steps have to be done:
The master verifies that the slave DMA channel is free by reading the DMA channel Control/
1.
Status register. This can be done using the X Memory Read procedure. If the DMA channel is
dedicated to this transfer, this step may be bypassed.
The master initializes the slave DMA channel. This can done by X Memory Write procedures
2.
or more efficiently using a predefined Host Command. If repetitive DMA transfers of data
blocks to a predefined address region will be done, the Host Command routine will contain just
two instructions: enable DMA channel and load the DMA Counter register.
The master initializes its own DMA channel.
3.
4.
The master initializes the slave HI.
The entire initialization process may take from less than 12 cycles up to more than a hundred cycles.
For example, in block DMA transfers in a linear array of 96Ks (transferring data only in one direction to fixed
predefined addresses), the initialization procedure may be executed only once. Each DMA block transfer
will demand just a DMA enable (bit set) and DMA Counter load for both master and slave processors. This
may be done in 8-12 cycles using fast interrupts.
The initialization process for system configuration with one master and N slaves is not much longer. If the
master makes "constant" DMA transfers then it may have N predefined interrupts while each slave DMA
has fixed control register setup. In this case, initialization may be done in less than 20 cycles.
7.5
DMA CONTROLLER
7.5.1 Introduction
The Direct Memory Access (DMA) Controller is an on-chip device that permits data transfers between any
two locations in any combination of memory spaces, without intervention of the DSP96002 core. Due to ded-
icated DMA buses and dual-access internal memories, a high level of isolation is achieved where the DMA
operation does not interfere or slow down the core operation. The DMA Controller has two channels, each
with its own register set. The DMA Controller registers are read/write registers memory-mapped in the in-
ternal I/O memory space (the highest 128 locations in X memory).
MOTOROLA
DSP96002 USER'S MANUAL
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