System Memory; Table 4-4 System Memory Options - Motorola CPCI-6115 Installation And Use Manual

System Memory

Table 4-3 MV64360 Power-Up Configuration Settings (continued)
Device AD
Bus Signal
WE[3:0],
DP[3:0]
BADR[0]
BADR[1]
BADR[2]
TxD0[6:1]
TxD0[7]
TxD1[1]
TxD1[4:2]
4.3.5 System Memory
The CPCI-6115 consists of up to three banks of Double-Data-Rate SDRAMs. DDR SDRAM
supports two data transfers per clock cycle. The base memory device is a standard monolithic
DDR SDRAM, 8-bits wide, in a 66-pin TSOPII package. The CPCI-6115 can be populated with
up to three banks of memory onboard (nine devices per bank). One or two banks can be
populated with standard single DDR devices. If three banks are populated, chip-stacking
technology is used on the top side to accommodate two banks in a single-bank footprint. When
using the stacked parts, the two stacked banks (0 and 2) are identical, so a single SPD
EEPROM is used for them.
All memory configurations operate at DDR226 (133 MHz CLK).

Table 4-4 System Memory Options

Organization
32 MB x 8
64 MB x 8
128 MB x 8
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Default
Select Power-Up
Option Setting
X X
Resistor 1
Resistor 1
Resistor 1
X X
Resistor 0
Resistor 0
Resistors 000
Memory Device
K4H560838F-TCB3 (133 MHz, CL=2.5)
K4H510838B-TCB3 (133 MHz, CL=2.5)
K4H1G0738M-TCB0 (133 MHz, CL=2.5)
K4H1G0838M-TCB0 (133 MHz, CL=2.5)
Description State of Bit vs. Function
DRAM PLL N X
Divider [7:4],
[3:0]
DRAM PLL NP X
DRAM PLL X
HIKVCO
DRAM PLL NP 0
1
DRAM PLL M X
Divider
JTAG Pad Calib 0
Bypass
1
Core PLL Bypass 0
1
Core PLL 000
Control
Functional Description
Not used in sync mode
Not used in sync mode
Not used in sync mode
PLL power down
PLL power up
(normal operation)
Not used in sync mode
Normal Operation
Bypass pad calibration
Normal Operation
Bypass the core's PLL
Tuning of the core PLL clock
tree.
Device
Size Bank Size
256 MB 256 MB
512 MB 512 MB
1 GB Two banks of
512 MB
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