Table of Contents
Advertisement
MV64360 System Controller
4.3.4.14 Board Reset Logic
The board reset logic is implemented in a programmable logic device (PLD) in order to provide
maximum flexibility of the circuit. Refer to
potential reset sources.
4.3.4.15 MV64360 MPP Configuration
The MV64360 contains a 32-bit multi-purpose port (MPP). The MPP pins can be configured as
general purpose I/O pins, as external interrupt inputs, or as specific control/status pins for one
of the MV64360 internal devices. After reset, all MPP pins default to general purpose inputs.
Software must then configure each of the pins for the desired function. The following table
defines the function assigned to each MPP pin on the CPCI-6115 board.
Table 4-2 MV64360 MPP Pin Function Assignments
MPP Pin
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Input/Output
Function
I
COM1 /COM2 interrupts (ORed)
I
Unused (optionally 21555 interrupt can be routed here)
I
Abort interrupt
I
RTC and Temperature Sensor interrupts (ORed)
I
Unused
I
Unused
I
MV64360 WDNMI# interrupt
I
BCM5421S PHY interrupts (ORed)
MPP[7:0] Interrupts
O
PCI Bus 1.0 - 21555 Bridge grant
I
PCI Bus 1.0 - 21555 Bridge request
O
PCI Bus 1.0 - PMC 1 secondary grant (GNTB#)
I
PCI Bus 1.0 - PMC 1 secondary request (REQB#)
O
PCI Bus 1.0 - PCI646U2 IDE Controller grant
I
PCI Bus 1.0 - PCI646U2 IDE Controller request
O
PCI Bus 1.0 - PMC 1 grant
I
PCI Bus 1.0 - PMC 1 request
MPP[15:8] PCI_1 Arbitration Request-Grant Pairs
I
PCI Bus 1.0 Interrupts - PMC1 INTA#, PMC1 INTC#, 21555
I
PCI Bus 1.0 Interrupts - PMC1 INTB#, PMC1 INTD#, IDE
I
PCI Bus 0.0 Interrupts - PMC2 INTA#, PMC2 INTC#
I
PCI Bus 0.0 Interrupts - PMC2 INTB#, PMC2 INTD#
I
CompactPCI Bus Interrupts - INTA#
I
CompactPCI Bus Interrupts - INTB#
Sources of Reset on page 86
Functional Description
for a summary of
75
Advertisement
Table of Contents
