Block Diagram; Figure 4-1 Cpci-6115 Baseboard Block Diagram - Motorola CPCI-6115 Installation And Use Manual

Functional Description
4.2

Block Diagram

The block diagram below illustrates the architecture of the CPCI-6115 baseboard.
Figure 4-1
Flash A
32MB
Flash B
8MB
NVRAM
RTC
M48T37V
Battery
COM2
COM1
PCI646U2
Controller
cPCI
68
CPCI-6115 Baseboard Block Diagram
L2 Cache
Processor
+
MPC7457
Private Memory
1MB/2MB
60x or MPX Bus 133 MHz
MV64360
System Controller
Device Bus
TL16550
UART
IDE
PHY PHY
cPCI
J5 J3
CPCI-6115 CompactPCI Single Board Computer Installation and Use (6806800A68D)
Init User
VPD SPD
I 2 C
DDR SDRAM
(3 bankS)
PCI/PCI-X
Bus 0.0, 64 bit
33/66/133 MHz
Single-wide PMC
(PMC2)
PMC2 I/O
33 bit, 33 MHz
PCI
Single-wide PMC
PMC1 I/O
(PMC1)
PHY
21555
Non-Transparent
PCI to PCI
Bridge
SROM
cPCI
J1/J2
Block Diagram
Front
Panel