Chapter 7. Tcp/Ip I/F Pwb Description - Sharp UP-600 Service Manual

CHAPTER 7. TCP/IP I/F PWB DESCRIPTION

1. GENERAL DESCRIPTION
This control board is an Ethernet board that supports TCP/IP proto-
col.
2. BLOCK DIAGRAM
/INTSR /INTHR
CN LOGIC
/INTSW /INTHW
/HWACK
/HRACK
/SWRQ
/SRRQ
/DPCS,
/CS2
/WR,/RD
Address
Dual-Port
Bus
RAM
4k byte
Data Bus
/CS3
LAN Cnt.
RJ-45
(8bit-Bus)
When writing data into FLASH, switch /CS0to EP-ROM and /CS3
to FLASH Memory.
10MHz
/CS0
/CS1
CPU
/CS2
(SH-2)
/CS3
/CS1
LD0~LD7
SRAM
128k byte
LA0~LA18
/CS0
LD0~LD7 LD0~LD7
FLASH
512k byte
LA0~LA11 LA0~LA18
/CS0
LD0~LD7 LD0~LD7
EP-ROM
(Writing in
to FLASH)
512k byte
LA0~LA19 LA0~LA18
3. CONFIGURATION
CPU :
[HitachiSH-2 Series SH7014 (20MHz)]
As external memory spaces, CS0 - CS3 and DRAM space are pro-
vided. This board assigns FLASH Memory to CS0, SRAM to CS1,
dual-port SRAM to CS2, and LAN controller to CS3.
LAN Controller : [RealtekRTL8019AS(20MHz)]
LAN controller is assigned to CS space.
Because of pseudo ISA connection, each register is assigned to ad-
dresses of H00C00300 and after.
ROM(FLASH Memory) :
[SharpLH28F004BVT(4Mbits)]
ROM (FLASH Memory) is assigned to CS0 space.
Data is written onto FLASH Memory from UV-EPROM by switching
the CSO space to UV-EPROM and the CS3 space to FALSH Mem-
ory.
MAC Address is written on FLASH Memory.
•
Company code is assigned to "08001FH".
•
The serial number and adjustment byte are stored in an area of 4
bytes from the address H'0007C000.
<The serial number is acquired according to Sharp's in-house
specification(SS).>
RAM : [S-RAM 1Mbits]
Assigned to CS1 space.
[IDT Dual-Port SRAM IDT7134]<Access Time=55ns>
Assigned to CS2 space.
The IDT7134 does not have any LOGICiBusy or Semaphorej, access
to the same address from both sides is inhibited.
Pulse Trans : [Pulse78Z034]
It is used for the 10Base-T standard and has a choke coil built in at
the output side.
<Access Time = 90ns>
<Access Time=70ns>