Sharp UP-600 Service Manual page 45

12. OPTION RAM INTERFACE
1) INTERFACE
The expanded RAM connector terminals are shown in the table.
The 40-pin RAM is used for the connector.
Extension RAM connector terminals
Signal Name Pin No.
+5V 1
HWR 3
GND 5
A20 7
A18 9
A16 11
A14 13
A12 15
A10 17
A8 19
A6 21
A4 23
A2 25
A0 27
D7 29
D5 31
D3 33
D1 35
RASPN2 37
GND 39
13. RESET SEQUENCE
The reset sequence block diagram is shown below. Note that RESET
signal (system reset) and CKDCR signal (CKDC reset) are different
from each other.
VCC
SLIDE
SW
CKDC9
STOP
CPU
RESET
(System reset)
MPCA9
IRQ0
Pin No. Signal Name
2 N.C.
4 N.C.
6 A21
8 A19
10 A17
12 A15
14 A13
16 A11
18 A9
20 A7
22 A5
24 A3
26 A1
28 RD
30 D6
32 D4
34 D2
36 D0
38 VCKDC
40 GND
CKDCR
(CKDC reset)
POFF
POFF
POWER
SUPPLY
INT0
1) POWER ON/OFF
The flow of signal processing at the time of the power supply turning
On/Off is as follows:
<Power OFF> Table 19
Power supply MPCA9
1 POFF L
2 IRQ0
3
4
<Power ON> Table 20
Power supply MPCA9
1 POFF H
2
3
The table below shows the timing chart.
Power supply On
+5V,+12V
PG GOOD
(POFF)
RESET
(System)
STOP
SHEN
SCK
8 PULSE
CPU CKDC9
L
STOP L
RESET L
(System reset)
CPU CKDC9
STOP H
RESET H
(System reset)
Power supply Off
10ms MIN