Toshiba TLCS-900/H1 Series Manual page 424

3.18.4 Operation in Each Mode
(1) 16-bit interval timer mode
Generating interrupts at fixed intervals.
In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The
interval time is set in the timer register TB0RG1H/L.
← 0
TB0RUN
← X
INTETB01
← 1
TB0FFCR
← 0
TB0MOD
← *
TB0RG1H/L
← 0
TB0RUN
X: Don't care, −: No change
(2) 16-bit programmable pulse generation (PPG) output mode
Square wave pulses can be generated at any frequency and duty ratio. The output
pulse may be either low active or high active.
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled
by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L
and is output to TB0OUT0. In this mode the following conditions must be satisfied.
(Value set in TB0RG0H/L) < (Value set in TB0RG1H/L)
Match with TB0RG0H/L
(INTTB00 inerrupt)
Match with TB0RG1H/L
(INTTB01 interrupt)
TB0OUT0 pin
Figure 3.18.6 Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low duty waves.
Match with TB0RG0H/L
Match with TB0RG1H/L
TB0RG0H/L
(Value to be compared)
Register buffer
7 6 5 4 3 2 1 0
−
0 X X 0 X 0
1 0 0 X 0 0 0
1 0 0 0 0 1 1
0 1 0 0 1
* *
(** = 01, 10, 11)
* * * * * * *
* * * * * * * *
−
0 X X 1 X 1
Up counter = Q
1
Q
1
Figure 3.18.7 Operation of Register Buffer
92CH21-422
Stop TMRB0.
Enable INTTB01 and set interrupt level 4. Disable INTTB00.
Disable the trigger.
Select internal clock for input and disable the capture function.
Set the interval time (16 bits).
Start TMRB0.
Up counter = Q
Shift into TB0RG1H/L
Q
Q
2
Write TB0RG0H/L
TMP92CH21
2
2
Q
3
2009-06-19