Toshiba TLCS-900/H1 Series Manual page 379

3.15.2 Control Registers
ALM Bit symbol
(1330H)
Read/Write
Reset State
Function
MELALMC Bit symbol
(1331H)
Read/Write
Reset State
Function Free-run counter control
00: Hold
01: Restart
10: Clear and stop
11: Clear and start
Note 1: MELALMC<FC1> is always read "0".
Note 2: When setting MELALMC register except <FC1:0> while the free-run counter is running, <FC1:0> is kept
"01".
MELFL Bit symbol
(1332H)
Read/Write
Reset State
Function
MELFH Bit symbol MELON
(1333H)
Read/Write
Reset State
Function
Control
melody
counter
0: Stop and
clear
1: Start
ALMINT Bit symbol
(1334H)
Read/Write
Reset State
Function
ALM Register
7 6
AL8 AL7 AL6
0 0 0
MELALMC Register
7 6 5
FC1 FC0 ALMINV
R/W R/W
0 0 0
Alarm
waveform
invert
1: Invert
MELFL Register
7 6
ML7 ML6 ML5
0 0 0
MELFH Register
7 6 5
R/W
0
ALMINT Register
7 6 5
R/W
Always
write "0"
92CH21-377
5 4 3
AL5 AL4
R/W
0 0
Setting alarm pattern
4 3
− −
0 0
Always write "0"
5 4 3
ML4 ML3
R/W
0 0
Setting melody frequency (Lower 8 bits)
4 3
ML11
0
Setting melody frequency (Upper 4 bits)
4 3
−
IALM4E IALM3E
0 0 0
1: Interrupt enable for INTALM4 to INTALM0
TMP92CH21
2 1
AL3 AL2
0 0
2 1
− −
R/W
0 0
2 1
ML2 ML1
0 0
2 1
ML10 ML9
R/W
0 0
2 1
IALM2E IALM1E
R/W
0 0
2009-06-19
0
AL1
0
0
MELALM
R/W
0
Output
waveform
select
0: Alarm
1: Melody
0
ML0
0
0
ML8
0
0
IALM0E
0