Toshiba TLCS-900/H1 Series Manual page 399

3.17.3 Operation Description
3.17.3.1 Accessing NAND-Flash Memory
The NDFC accesses data on NAND Flash memory indirectly through its internal
registers. It also contains the ECC calculating circuits. Please see 3.17.3.2 for details
of the ECC. This section explains the operations for accessing the NAND Flash.
Basically, set the command in ND0FMCR and then read or write to ND0FDTR. The
read cycle for ND0FDTR is completed after the external read cycle for the
NAND-Flash is finished. Likewise, the write cycle for ND0FDTR is completed after
the external write cycle for the NAND-Flash is finished.
1) Initialize
The initialize sequence is as follows.
(1) ND0FSPR: Set the low pulse width.
(2) ND0FIMR: Set 0x81 if interrupt is required.
2) Write
The write sequence is as follows.
(1) ND0FMCR:
(2) Write 512 bytes
(3) Read ECC data
(Release interrupt mask)
Set 0x7C for ECC data reset.
ND0FMCR: Set 0x9D for NDCLE signal enable and command mode.
ND0FDTR: Set 0x80 for the serial data input command.
ND0FMCR: Set 0x9E for NDALE signal enable and address mode.
ND0FDTR: Write address. Set A [7:0], A [16:9], and A [24:17]. If it is
required, set A [25].
ND0FMCR: Set 0xBC for the data mode.
ND0FDTR: Write 512 bytes data.
ND0FMCR: Set 0xDC for the ECC data read mode.
NDECCRD: Read 6 bytes ECC data.
First data: LPR [7:0]
Second data: LPR [15:8]
Third data: CPR [5:0], 2'b11
Fourth data: LPR [23:16]
Fifth data: LPR [31:24]
Sixth data: CPR [11:6], 2'b11
92CH21-397
TMP92CH21
2009-06-19