Toshiba TLCS-900/H1 Series Manual page 347

• 256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits)
Display memory image
Address 0
LSB
D0
0 1 2 3 4 5
R1 G1
Address 4
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R5 G5
LD bus output sequence
4-bit width A type
→ 13-11 (G2) ...
LD0 2-0 (R1)
→ 15-14 (B2) ...
LD1 5-3 (G1)
→ 18-16 (R3) ...
LD2 7-6 (B1)
→ 21-19 (G3) ...
LD3 10-8 (R2)
LD4 Not used
LD5 Not used
LD6 Not used
LD7 Not used
LD bus output sequence
8-bit width A type
→ 23-22 (B3) ...
LD0 2-0 (R1)
→ 26-24 (R4) ...
LD1 5-3 (G1)
→ 29-27 (G4) ...
LD2 7-6 (B1)
→ 31-30 (B4) ...
LD3 10-8 (R2)
13-11 (G2) → 34-32 (R5) ...
LD4
15-14 (B2) → 37-35 (G5) ...
LD5
18-16 (R3) → 39-38 (B5) ...
LD6
21-19 (G3) → 42-40 (R6) ...
LD7
* This mode is not supported by 4-bit width B type.
Figure 3.14.4 Relation of Memory Map Image and Output Data (3)
Address 1
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B1 R2 G2
Address 5
B5 R6 G6
8-bit width B type
LD0 2-0 (R1)
LD1 5-3 (B1)
LD2 13-11 (G2)
LD3 18-16 (R3)
LD4 23-22 (B3)
LD5 29-27 (G4)
LD6 34-32 (R5)
LD7 39-38 (B5)
92CH21-345
Address 2
B2 R3 G3
Address 6
B6 R7 G7
→ 7-6 (G1) →
→ 10-8 (R2) →
→ 15-14 (B2) →
→ 21-19 (G3) →
→ 26-24 (R4) →
→ 31-30 (B4) →
→ 37-35 (G5) →
→ 42-40 (R6) →
TMP92CH21
Address 3
B3 R4 G4
Address 7
B7 R8 G8
→ 47-46 (B6)
45-43 (G6)
→ 53-51 (G7)
50-48 (R7)
→ 58-56 (R8)
55-54 (B7)
→ 63-62 (B8)
61-59 (G8)
→ 69-67 (G9)
66-64 (R9)
→ 74-72 (R10) ...
71-70 (B9)
77-75 (G10) → 79-78 (B10) ...
82-80 (R11) → 85-83 (G11) ...
2009-06-19
MSB
D31
B4
MSB
D31
B8
...
...
...
...
...