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Footnotes indicate when to account for the appropriate effective address times.
The total number of clock cycles is outside the parenthe$es. The numbers
inside parentheses (r/p/w) are included in the total clock cycle number. All
timing data assumes two-clock reads and writes.
Instruction
Head
e:
Tall
Cycles
EXG
Rn,Rm
2
0
4(0/1/0)
MOVEC
Cr, Rn
10
0
14(0/2/0)
MOVEC
Rn, Cr
12
0
14-16(0/1/0)
MOVE
CCR, On
2
0
4(0/1/0)
MOVE
CCR, (CEA)
0
2
4(0/1/1 )
MOVE
On,CCR
2
0
4(0/1/0)
MOVE
(FEA), CCR
0
0
4(0/1/0)
MOVE
SR,On
2
0
4(0/1/0)
MOVE
SR, (CEA)
0
2
4(0/1/1 )
MOVE
On,SR
4
-2
10(0/3/0)
MOVE
(FEA), SR
0
-2
10(0/3/0)
MOVEM.W
(CEA), RL
1
0
8
+
n
*
4 (n
+
1, 2, 0)
1
MOVEM.W
RL, (CEA)
1
0
8
+
n
*
4 (0, 2, n)
1
MOVEM.L
(CEA), RL
1
0
12 + n
*
4(2n
+
2, 2, 0)
MOVEM.L
RL, (CEA)
1
2
10+ n ·4 (0, 2, 2n)
MOVEP.W
On, (d16, An)
2
0
10(0/2/2)
MOVEP.W
(d16, An), On
1
2
11 (2/2/0)
MOVEP.L
On, (d16, An)
2
0
14(0/2/4)
MOVEP.L
(d16, An), On
1
2
19(4/2/0)
MOVES (Save)
(CEA), Rn
1
1
3(0/1/0)
MOVES (Op)
(CEA), Rn
7
1
11 (X11/0)
MOVES (Save)
Rn, (CEA)
1
1
3(0/1/0)
MOVES (Op)
Rn, (CEA)
9
2
12(0/1/X)
MOVE
USP, An
0
0
2(0/1/0)
MOVE
An, USP
0
0
2(0/1/0)
SWAP
On
4
0
6(0/1/0)
X = There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
lEach bus cycle may take up to four clocks without increasing total execution time.
Cr= Control registers USP, VBR, SFC, and OFC
n = Number of registers to transfer
RL
=
Register List
< = Maximum time - certain data or mode combinations may execute faster.
NOTE: The MOVES instruction has an additional a save step which other instructions do not
have. To calculate total the instruction time, calculate the Save, the effective
address, and the Operation execution times, and combine in the order listed, using
the equations given in
8.1.6
Instruction Execution Time Calcuation.
CPU32 REFERENCE MANUAL
INSTRUCTION EXECUTION
TIMING
MOTOROLA
8-17
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