Lin-Uart Extended Status Control Register (Escr) - Fujitsu 8FX Hardware Manual

CHAPTER 14 LIN-UART
14.7 Registers
14.7.5 LIN-UART Extended Status Control Register
(ESCR)
The LIN-UART extended status control register (ESCR) has the settings for
enabling/disabling LIN synch break interrupt, LIN synch break length selection,
LIN synch break detection, direct access to the SIN and SOT pins, continuous
clock output in LIN-UART synchronous clock mode and sampling clock edge.
■ Register Configuration
bit 7
Field LBIE
Attribute R/W
Initial value 0
■ Register Functions
[bit7] LBIE: LIN synch break detection interrupt enable bit
This bit enables or disables LIN synch break detection interrupts.
An interrupt is generated when the LIN synch break detection flag (LBD) is "1" and the interrupt is enabled
(LBIE = 1).
This bit is fixed at "0" in operating mode 1 and operating mode 2.
bit7
Writing "0"
Writing "1"
[bit6] LBD: LIN synch break detection flag bit
This bit detects the LIN synch break.
This bit is set to "1" when a LIN synch break is detected in operating mode 3 (the serial input is "0" when bit
width is 11 bits or more). If "0" is written to the LBD bit, the LBD bit and the interrupt are cleared. Although
the bit always returns "1" if read by the read-modify-write (RMW) type of instruction, this does not indicate
that a LIN synch break has been detected.
bit6
Reading "0"
Writing "1"
Writing "0"
Writing "1"
Note: To detect a LIN synch break, enable the LIN synch break detection interrupt (LBIE = 1), and then
disable the reception (SCR:RXE = 0).
252
6 5
LBD LBL1
R/W R/W
0 0
Disables the LIN synch break detection interrupt.
Enables the LIN synch break detection interrupt.
Indicates that no LIN synch break has been detected.
Indicates that a LIN synch break has been detected.
Clears this bit.
Has no effect on operation.
FUJITSU SEMICONDUCTOR LIMITED
4 3
LBL0 SOPE
R/W R/W
0 0
Details
Details
MB95630H Series
2 1
SIOP CCO
R/W R/W
1 0
MN702-00009-2v0-E
0
SCES
R/W
0