Lin-Uart Serial Control Register (Scr) - Fujitsu 8FX Hardware Manual

CHAPTER 14 LIN-UART
14.7 Registers
14.7.1

LIN-UART Serial Control Register (SCR)

The LIN-UART serial control register (SCR) is used to set parity, select the stop
bit length and data length, select the frame data format in operating mode 1,
clear the receive error flag, and enable/disable transmission/reception.
■ Register Configuration
bit 7
Field PEN
Attribute R/W
Initial value 0
■ Register Functions
[bit7] PEN: Parity enable bit
This bit specifies whether or not to add (at transmission) and detect (at reception) a parity bit.
bit7
Writing "0"
Writing "1"
Note: The parity bit is added only in operating mode 0, or in operating mode 2 in which the start/stop bits
are to be added to the synchronous data format (ECCR:SSM = 1). This bit is fixed at "0" in operating
mode 3 (LIN).
[bit6] P: Parity select bit
With the parity bit having been enabled (SCR:PEN = 1), setting this bit to "1" selects the odd parity and
setting this bit to "0" selects the even parity.
bit6
Writing "0"
Writing "1"
[bit5] SBL: Stop bit length select bit
This bit sets the bit length of the stop bit (frame end mark in transmit data) in operating mode 0, 1
(asynchronous) or in operating mode 2 (synchronous) in which the start/stop bits are to be added to the
synchronous data format (ECCR:SSM = 1).
This bit is fixed at "0" in operating mode 3 (LIN).
bit5
Writing "0"
Writing "1"
Note: At reception, only a framing error for the bit length of the stop bit is always detected.
244
6 5
P SBL
R/W R/W
0 0
Disables parity.
Enables parity.
Even parity
Odd parity
1 bit
2 bits
FUJITSU SEMICONDUCTOR LIMITED
4 3
CL AD
R/W R/W
0 0
Details
Details
Details
MB95630H Series
2 1
CRE RXE
R/W R/W
0 0
MN702-00009-2v0-E
0
TXE
R/W
0