Interrupt Processing - Fujitsu 8FX Hardware Manual

MB95630H Series
5.1.2

Interrupt Processing

When an interrupt request is made by a peripheral function, the interrupt
controller notifies the CPU of the interrupt level of that interrupt request. When
the CPU is ready to accept interrupts, it halts the program it is executing and
executes an interrupt service routine.
■ Interrupt Processing
The procedure for processing an interrupt is as follows: the generation of an interrupt source in a
peripheral function, the execution of the main program, the setting of the interrupt request flag bit,
the checking of the interrupt request enable bit, the determination of the interrupt level (ILR0 to
ILR5 and CCR:IL[1:0]), the checking for interrupt requests of the same interrupt level made
simultaneously, and the checking of the interrupt enable flag (CCR:I).
Figure 5.1-1 shows the interrupt processing.
START
(1)
Initialize peripheral resources
Interrupt
from peripheral
resource?
NO
(2) Execute main program
(7) Restore PC and PS
MN702-00009-2v0-E
Figure 5.1-1 Interrupt Processing
(7)
RAM
(6)
YES
(3)
Peripheral
resource interrupt request
YES
output enabled?
Determine interrupt priority and
NO
(4)
transfer interrupt level to CPU
Compare interrupt level
with IL bit in PS
Interrupt level higher
than IL value?
NO
Interrupt service routine
Clear interrupt request
Execute interrupt processing
RETI
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 5 INTERRUPTS
Condition code register (CCR)
I
CPU Check
(5)
Interrupt request
flag
AND
Interrupt request
enabled
(3)
Each peripheral resource
YES
YES
I flag = 1?
NO
Save PC and PS to stack
(6) PC interrupt vector
Update IL in PS
5.1 Interrupts
IL
Comparator
Release from stop mode
Release from sleep mode
Release from time-base
timer mode or watch mode
(4)
Interrupt
controller
(5)
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