Table of Contents
Advertisement
Chapter 46 Alarm Comparator
3.Alarm Comparator Control/Status Register (ACSR)
3. Alarm Comparator Control/Status Register (ACSR)
• ACSR0 (ch0): Address 01AD
• ACSR1 (ch1): Address 01AF
Address
ACSR0 0000 01AD
ACSR1 0000 01AF
Figure 3-1 Structure of Alarm comparator control/status register
Bit 7: MD Mode select
Bit 6: OV_EN Overvoltage Enable
Bit 5: UV_EN Undervoltage Enable
Bit 4: OUT2 synchronized output of Alarm comparator UV output.
Bit 3: OUT1 synchronized output of Alarm comparator OV output.
Bit 2: IRQ Interrupt bit.
918
(Access:
Byte
H
(Access:
Byte
H
7
6
5
H
MD
OV_EN
UV_EN
H
R/W
R/W
R/W
1
Fast mode enabled
0
Slow mode enabled
1
Interrupt enabled in case of overvoltage.
0
No interrupt in case of overvoltage
1
Interrupt enabled in case of undervoltage
0
No interrupt in case of undervoltage.
0
analog input voltage < 2/5 AVDD
1
analog input voltage > 2/5 AVDD
1
analog input voltage > 4/5 AVDD
0
analog input voltage < 4/5 AVDD
1
Under- or overvoltage condition detected
0
Normal operation
)
)
Bits
4
3
2
OUT2
OUT1
IRQ
R
R
R/W
1
0
Initial value
011XXX00
IEN
PD
R/W
R/W
Access
[Initial value]
[Initial value]
[Initial value]
B
Advertisement
Table of Contents
