Port 1 Register - Fujitsu Semiconductor Controller MB89950/950A Hardware Manual

CHAPTER 4 I/O PORTS
I Block diagram of port 1 pins
PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
PDR write
SPL: Pin state specification bit in the standby control register (STBC)
I Port 1 register
The port 1 register consists of PDR1. Each bit in the register has a one-to-one relationship with a port 1 pin.
Table 4.3-2 "Correspondence between pin and register for port 1" shows the correspondence between the
pins and register for port 1.
Table 4.3-2 Correspondence between pin and register for port 1
Port
Port 1
78
Figure 4.3-1 Block diagram of port 1 pins
LCD segment driver output
Output latch
Stop mode (SPL = 1)
Correspondence between register bit and pin
PDR1 Bit 7
Corresponding pin P17
Mask option
Segment driver output select register
Stop mode (SPL = 1)
Bit 6 Bit 5 Bit 4
P16 P15 P14
Pin
N-ch
Bit 3 Bit 2 Bit 1
P13 P12 P11
Bit 0
P10