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CHAPTER 4 I/O PORTS
4.2.1
Port 0 Data Register (PDR0)
This section describes the port 0 data register.
I Port 0 data register functions
G
Port 0 data register (PDR0)
The PDR0 register holds the pin states. Therefore, a bit corresponding to a pin set as an output port can be
read as the same state ("0" or "1") as the output latch, but when it is an input port, it cannot be read as the
output latch state.
Reference:
For SETB and CLRB bit operation instructions, since the state of output latch (not the pin) is read, the
output latch states of bits other than those being operated on are not changed.
G
Settings as an LCD segment driver output
To use pins as LCD segment driver outputs, segment driver output must be selected by the mask option.
Furthermore, the segment driver output select register must be set to the same as the mask option, so that
the CMOS input port can be protected.
Table 4.2-3 "Port 0 data register function" a lists the functions of the port 0 data register.
Table 4.2-3 Port 0 data register function
Register
Data
0
Port 0 data
register (PDR0)
1
R/W: Readable and writable
74
Read
Outputs an "L" level to the pin.
Pin state is the
(Sets "0" to the output latch and
"L" level.
turn the output transistor "ON".)
Sets the pin to the high-
Pin state is the
impedance state.
"H" level.
(Sets "1" to the output latch and
turn the output transistor "OFF".)
Read/
Write
Write
R/W
Address
Initial value
0000
11111111
H
B
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