Page 1 CM25-10153-2E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89202/F202RA Series HARDWARE MANUAL...
Page 3 Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL:http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED...
Page 5 The F MC-8L Programming Manual contains details of the programming instructions. Note: F MC, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU LIMITED. ■ Trademark The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Page 6 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) This chapter describes the functions and operation of external interrupt circuit 1 (edge). CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) This chapter describes the functions and operation of external interrupt circuit 2 (level). CHAPTER 12 A/D CONVERTER This chapter describes the functions and operation of the A/D converter.
Page 7 FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information.
Page 8 READING THIS MANUAL ■ Example Notation of Register Names and Pin Names ❍ Example notation of register names and bit names By writing 1 into the sleep bit of the standby control register (STBC : SLP), ... Prohibit the output of interrupt request of the time-base timer (TBTC : TBIE = 0). If interrupt enabled (CCR : I = 1) is specified, the interrupt is accepted.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ... 1 Features of MB89202/F202RA Series ... 2 MB89202/F202RA Series Product Lineup ... 4 Differences between Models ... 6 Block Diagram of MB89202/F202RA Series ... 7 Pin Assignment ... 8 Package Dimensions ... 10 Pin Functions Description ... 12 I/O Circuit Types ...
Page 10 3.7.4 Standby Control Register (STBC) ... 66 3.7.5 Diagram for State Transition in Standby Mode ... 68 3.7.6 Notes on Standby Mode ... 70 Memory Access Mode ... 72 CHAPTER 4 I/O PORTS ... 75 Overview of I/O Ports ... 76 Port 0 ...
Page 11 CHAPTER 7 8-BIT PWM TIMER ... 135 Overview of 8-bit PWM Timer ... 136 Configuration of 8-bit PWM Timer ... 139 Pin of 8-bit PWM Timer ... 141 Registers of 8-bit PWM Timer ... 142 7.4.1 PWM Control Register (CNTR) ... 143 7.4.2 PWM Compare Register (COMR) ...
Page 12 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ... 225 10.1 Overview of External Interrupt Circuit 1 ... 226 10.2 Configuration of External Interrupt Circuit 1 ... 227 10.3 Pins of External Interrupt Circuit 1 ... 229 10.4 Registers of External Interrupt Circuit 1 ... 231 10.4.1 External Interrupt Control Register 1 (EIC1) ...
Page 13 13.4.7 Serial Switch Register (SSEL) ... 301 13.5 Interrupt of UART ... 303 13.6 Operations of UART Functions ... 304 13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3) ... 306 13.6.2 Reception Operations (Operating Mode 0, 1, or 3) ... 307 13.6.3 Reception Operations (Operating Mode 2 Only) ...
Page 14 CHAPTER 17 FLASH MEMORY ... 357 17.1 Overview of Flash Memory ... 358 17.2 Flash Memory Control Status Register (FMCS) ... 359 17.3 Starting the Flash Memory Automatic Algorithm ... 361 17.4 Confirming the Automatic Algorithm Execution State ... 362 17.4.1 Data Polling Flag (DQ7) ...
Page 15 Main changes in this edition Page 1.3 Differences between Models 1.7 Pin Functions 2.1 Precautions on Handling Devices 3.1.1 Specific-purpose Areas 3.5 Reset 3.6.3 System Clock Control Register (SYCC) 6.3 Watchdog Control Register (WDTC) 8.6 Explanation of Operations of Interval Timer Functions 12.3 Pins of A/D Converter...
Page 16 Page 13.6.3 Reception Operations (Operating Mode 2 Only) 17.1 Overview of Flash Memory 17.5.2 Writing Data B.4 F MC-8L Instructions List The vertical lines marked in the left side of the page show the changes. Changes (For details, refer to main body.) "■...
Page 17: Chapter 1 Overview
CHAPTER 1 OVERVIEW This chapter describes the features and basic specification of the MB89202/F202RA series. 1.1 Features of MB89202/F202RA Series 1.2 MB89202/F202RA Series Product Lineup 1.3 Differences between Models 1.4 Block Diagram of MB89202/F202RA Series 1.5 Pin Assignment 1.6 Package Dimensions 1.7 Pin Functions Description 1.8 I/O Circuit Types...
Page 18: Features Of Mb89202/F202Ra Series
CHAPTER 1 OVERVIEW Features of MB89202/F202RA Series The MB89202/F202RA series contains general-purpose single-chip microcontrollers that incorporate a full range of peripheral functions such as A/D converter, UART, PWM timer, PPG, capture timer/counter and external interrupts as well as a compact instruction set.
Page 19 External interrupt 2 (level detection × 8 pins, 1 channel) has eight independent inputs and can be used • for wake-up from low-power consumption mode. (L level detection function is supported.) ● Low-power consumption modes (standby modes) • Stop mode (The oscillation is stopped so that current consumption is minimal.) •...
Page 20: Mb89202/F202Ra Series Product Lineup
CHAPTER 1 OVERVIEW MB89202/F202RA Series Product Lineup Four MB89202 series models are available. Table 1.2-1 shows the models and Table 1.2- 2 shows the CPU and peripheral functions. ■ MB89202/F202RA Series Models Table 1.2-1 MB89202/F202RA Series Models Evaluation product Classification (for development) 32K ×...
Page 21 Table 1.2-2 CPU and Peripheral Functions of MB89202/F202RA Series Item Number of basic instructions: Instruction bit length: Instruction length: CPU function Data bit length: Minimum instruction execution time: Interrupt processing time: General-purpose I/O port: 26 pins (Also serve as peripherals. 4 of which can be used as N-ch Port 21-bit 21 bits...
Page 22: Differences Between Models
CHAPTER 1 OVERVIEW Differences between Models This section describes the precautions to be taken when selecting a MB89202/F202RA series model. ■ Precautions when Selecting a Model Table 1.3-1 Differences between Models Package DIP-32P-M06 FPT-32P-M03 FPT-64P-M03 ● Current consumption • When operated at a low speed, the current consumption of a model with a flash is greater than that of a model with a mask ROM, though the current consumption in sleep or stop mode is the same.
Page 23: Block Diagram Of Mb89202/F202Ra Series
Block Diagram of MB89202/F202RA Series Figure 1.4-1 shows the block diagram of the MB89202/F202RA series. ■ Block Diagram of MB89202/F202RA Series Figure 1.4-1 Block Diagram of MB89202/F202RA Series P60, P61 P04 / INT24 P07 / INT27 P02 / INT22 / AN6, P03 / INT23 / AN7 P00 / INT20 / AN4, P01 / INT21 / AN5...
Page 24: Pin Assignment
CHAPTER 1 OVERVIEW Pin Assignment Figure 1.5-1 and Figure 1.5-2 show the pin assignment of the MB89202/F202RA series. ■ Pin Assignment of DIP-32P-M06 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 P33/EC * : Large-current drive type Figure 1.5-1 Pin Assignment of DIP-32P-M06 P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5...
Page 25 ■ Pin Assignment of FPT-34P-M03 Figure 1.5-2 Pin Assignment of FPT-34P-M03 P04/INT24 P05/INT25 P06/INT26 P07/INT27 P37/BZ/PPG P36/INT12 P35/INT11 P34/TO/INT10 * : Large-current drive type Note: N.C.: Do not use because it is connected internally. P33/EC N.C. CHAPTER 1 OVERVIEW P03/INT23/AN7 P02/INT22/AN6 P01/INT21/AN5 P00/INT20/AN4...
Page 26: Package Dimensions
3.30 –0.30 +.008 .130 –.012 1.27(.050) MAX. 2003 FUJITSU LIMITED D32018S-c-1-1 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html Lead pitch Low space Sealing method Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness.
Page 27: Chapter 1 Overview
34-pin plastic SSOP (FPT-34P-M03) 34-pin plastic SSOP (FPT-34P-M03) 11.00±0.10(.433±.004) INDEX 0.65(.0265) 0.10(.004) 0.10(.004) 2003 FUJITSU LIMITED F34003S-c-2-3 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html Lead pitch Package width × package length Lead shape Sealing method Mounting height Code P-SSOP34-6.1×11-0.65...
Page 28: Pin Functions Description
CHAPTER 1 OVERVIEW Pin Functions Description Table 1.7-1 describes the I/O pins and functions. The letters in the circuit type column shown in Table 1.7-1 correspond to the letters in the Circuit Type column shown in Table 1.8-1 . ■ Pin Functions Description Table 1.7-1 Pin Functions Description (1/2) Pin No.
Page 29 Table 1.7-1 Pin Functions Description (2/2) Pin No. name SHDIP32 SSOP34 P32/UI/ P33/EC P34/ INT10 P35/ INT11 P36/ INT12 P37/ P50/ 24 to 27 26 to 29 P40/ AN0 to P43/ 21 to 23 23 to 25 P70 to 16, 22 N.C.
Page 30: I/O Circuit Types
CHAPTER 1 OVERVIEW I/O Circuit Types Table 1.8-1 describes the I/O circuit types. The letters in the circuit column shown in Table 1.8-1 correspond to the letters in the circuit type column shown in Table 1.7-1 . ■ I/O Circuit Types Table 1.8-1 I/O Circuit Types (1/2) Types Standby control signal...
Page 31 Table 1.8-1 I/O Circuit Types (2/2) Types P-ch Input enable Input enable P-ch Input enable Input enable A/D enable P-ch Input enable Input enable A/D enable Input enable Circuit CMOS output CMOS input Hysteresis input (Resource input) Pull-up resistor optional P-ch N-ch Port...
Page 32 CHAPTER 1 OVERVIEW...
Page 33: Chapter 2 Handling Devices
CHAPTER 2 HANDLING DEVICES This chapter describes the precautions to be taken when handling general-purpose one-chip microcontrollers. 2.1 Precautions on Handling Devices...
Page 34: Precautions On Handling Devices
CHAPTER 2 HANDLING DEVICES Precautions on Handling Devices This section describes the precautions to be taken when handling the power supply voltage, pins, and other device items. ■ Precautions on Handling Devices ● Ensure that the voltage does not exceed the maximum ratings. (Preventing latch-up) A latch-up may occur if a voltage higher than Vcc or lower than Vss is applied to input or output pins other than middle- or high-level resistant pins, or if voltage exceeding the rated value is applied between Vcc and Vss.
Page 35 ● Note to Noise in the External Reset Pin (RST) If the reset pulse applied to the external reset pin (RST) does not meet the specifications, it may cause malfunctions. Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin (RST).
Page 36 CHAPTER 2 HANDLING DEVICES Figure 2.1-1 Operation Sequences after Power-on Reset between Product Types Power supply (V CPU operation of product with a step-down circuit (MB89F202/F202RA) CPU operation of product without a step-down circuit (MB89202 and MB89V201) : Main oscillation frequency As shown in Figure 2.1-1 , the start of CPU operation of a product with a step-down circuit is slower than that of the product without a step-down circuit.
Page 37: Chapter 3 Cpu
CHAPTER 3 This chapter describes the functions and operations of the CPU. 3.1 Memory Space 3.2 Dedicated Register 3.3 General-Purpose Registers 3.4 Interrupts 3.5 Reset 3.6 Clock 3.7 Standby Mode (Low-Power Consumption Mode) 3.8 Memory Access Mode...
Page 38: Memory Space
CHAPTER 3 CPU Memory Space The MB89202/F202RA series has 64-KB memory space that consists of the I/O area, RAM area, ROM area, and external area. Part of the memory space is applied for specific use such as general-purpose registers or a vector table. ■...
Page 39: Memory Map
■ Memory Map MB89V201 0000 0080 RAM 512 bytes 0100 0200 0280 Not available 8000 External EPROM 32 KB FFFF Figure 3.1-1 Memory Map MB89202 0000 0000 0080 0080 RAM 512 bytes 0100 0100 0200 0200 0280 0280 Not available C000 C000 ROM 16 KB...
Page 40: Specific-Purpose Areas
CHAPTER 3 CPU 3.1.1 Specific-purpose Areas In addition to the I/O area, the general-purpose register area and vector table area are available as areas for specific applications. ■ General-purpose Register Area (Address: 0100 • This area is used for 8-bit arithmetic operations and transfer. Supplementary registers are provided. •...
Page 41 Table 3.1-1 Vector Table (2/2) Vector call instruction IRQB IRQA IRQ9 IRQ8 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Mode data Reset vector *: For MB89202 / MB89V201, FFFC For MB89F202/F202RA, write "01 otherwise write "FF ". Address in the vector table Upper digits Lower digits FFE4...
Page 42: Location Of 16-Bit Data On Memory
CHAPTER 3 CPU 3.1.2 Location of 16-bit Data on Memory Upper digits of 16-bit data and stack data are stored in lower addresses on memory. ■ 16-bit Data Storage State on RAM When 16-bit data is written into RAM, the upper byte of the data is stored with a lower address and the lower byte of the data is stored with the next address.
Page 43: Dedicated Register
Dedicated Register The dedicated register in the CPU consists of a program counter (PC), two arithmetic operation registers (A and T), three address pointers (IX, EP, and SP), and program status (PS) register. The size of each register is 16 bits. ■...
Page 44 CHAPTER 3 CPU ● Temporary Accumulator (T) The temporary accumulator is an auxiliary 16-bit arithmetic operation register. It handles arithmetic operations using data in the accumulator (A). When arithmetic operations in the accumulator (A) are handled in word units (16 bits), data in the temporary accumulator is handled in word units. Otherwise, it is handled in byte units (8 bits).
Page 45: Condition Code Register (Ccr)
3.2.1 Condition Code Register (CCR) The condition code register (CCR) is the lower 8 bits of the program status register (PS). The condition code register consists of bits (C, V, Z, N, and H) for indicating the results of arithmetic operations or data to be transferred and control bits (I, IL1, and IL0) for controlling the acceptance of interrupt requests.
Page 46 CHAPTER 3 CPU Figure 3.2-3 shows how the shift commands change the carry flag. Figure 3.2-3 Change of the Carrier Flag by the Shift Commands - Shift to the left (ROLC) Note: The condition code register is part of the program status register (PS), and thus is not allowed to access only the condition code register.
Page 47: Register Bank Pointer (Rp)
3.2.2 Register Bank Pointer (RP) The register bank pointer (RP) is the upper 8 bits of the program status register (PS). The register bank pointer indicates the general-purpose register bank address being used, and the address is converted to the actual address in general-purpose register addressing.
Page 48: General-Purpose Registers
CHAPTER 3 CPU General-Purpose Registers The general-purpose registers are memory blocks. Eight 8-bits comprise a bank. The register bank pointer (RP) specifies a register bank. Although up to 32 banks can be used, some banks can be expanded onto external RAM if the capacity of internal RAM is not sufficient for all 32 banks.
Page 49: Features Of The General-Purpose Registers
■ Features of the General-purpose Registers The general-purpose registers have the following features: • High-speed access with short instructions (general-purpose register addressing) • Register banks (in blocks) that allow data to be easily conserved and partitioned in the unit of function The general-purpose registers allow specific register banks to be statically assigned with the interrupt processing routine or vector call (CALLV #0 to #7) processing routine.
Page 50: Interrupts
CHAPTER 3 CPU Interrupts The MB89202/F202RA series supports 12 interrupt request inputs corresponding to peripheral functions and allows an interrupt level to be assigned to each of the inputs. The interrupt controller compares levels of interrupts generated by peripheral functions when output of interrupt requests is allowed for peripheral functions.
Page 51 Table 3.4-1 Interrupt Requests and Interrupt Vectors (2/2) Interrupt request IRQB (Flash interface) IRQC (8-bit serial I/O) IRQD (Unused) IRQE (Unused) IRQF (Unused) Address in the Names of bits in vector table the interrupt level setting Upper Lower registers digits digits FFE4 FFE5...
Page 52: Interrupt Level Setting Registers (Ilr1 To Ilr4)
CHAPTER 3 CPU 3.4.1 Interrupt Level Setting Registers (ILR1 to ILR4) For the interrupt level setting registers (ILR1, 2, 3, and 4), 16 two-bit data items corresponding to interrupt requests sent from peripheral functions are assigned. Interrupt levels can be specified in these 2-bits (interrupt level setting bits). ■...
Page 53: Steps In The Interrupt Operation
3.4.2 Steps in the Interrupt Operation When an interrupt request is generated in a peripheral function, the interrupt controller notifies the CPU of its interrupt level. If the CPU can accept an interrupt, the CPU temporarily stops the program that is handling and starts the interrupt processing routine.
Page 54 CHAPTER 3 CPU ➃ The interrupt controller is always monitoring interrupt requests from peripheral functions. The interrupt controller notifies the CPU of the highest interrupt level interrupt among levels corresponding to interrupt requests currently generated. If different requests are made with the same interrupt level, the interrupt controller also determines their priorities.
Page 55: Multiple Interrupts
3.4.3 Multiple Interrupts Multiple interrupts are allowed by setting different levels into the interrupt level setting registers (ILR1 to ILR4) for multiple interrupt requests from peripheral functions. ■ Multiple Interrupts When an interrupt request with a higher interrupt level is generated while the interrupt processing routine is operating, the current interrupt processing cycle is stopped to accept the higher-level interrupt request.
Page 56: Interrupt Processing Time
CHAPTER 3 CPU 3.4.4 Interrupt Processing Time From when an interrupt request is generated to when control is transferred to the interrupt processing routine, both the time to quit the instruction being executed and the time to manage the interrupt (required to prepare interrupt processing) are required. The total time must be within 30 instruction cycles.
Page 57: Stack Operation At Interrupt Processing
3.4.5 Stack Operation at Interrupt Processing This section describes how values in registers are saved and restored at interrupt processing. ■ Stack Operation at the Beginning of Interrupt Processing After accepting an interrupt, the CPU automatically saves the values in the program counter (PC) and program status (PS) in the stack.
Page 58: Stack Area For Interrupt Processing
CHAPTER 3 CPU 3.4.6 Stack Area for Interrupt Processing A stack area on RAM is used for interrupt processing. The value in the stack pointer (SP) is used as the start address of the stack area. ■ Stack Area for Interrupt Processing The stack area is used to save/restore the value in the program counter (PC) when executing the subroutine call instruction (CALL) or vector call instruction (CALLV) or temporarily save and restore values in registers or other storage with the PUSHW and POPW instruction.
Page 59: Reset
Reset There are four sources of reset: • External reset • Software reset • Watchdog reset • Power-on reset Oscillation stabilization wait time is not applied in some operating modes when a reset occurs or in some option settings. ■ Reset Sources Table 3.5-1 Reset Sources Reset source...
Page 60 CHAPTER 3 CPU ● Power-on reset Power-on reset occurs when power is turned on. Power-on reset occurs after oscillation stabilization wait time has expired. Power-on reset requires an external reset circuit. ■ Reset Sources and Oscillation Stabilization Wait Time Operations in oscillation stabilization wait time depend on the operating mode used when a reset occurs. After a reset, active mode is set regardless of the operating mode applied before the reset (standby mode) and reset source.
Page 61: Reset Flag Register (Rsfr)
3.5.1 Reset Flag Register (RSFR) The reset flag register (RSFR) allows confirmation of the source for a generated reset. ■ Configuration of the Reset Flag Register (RSFR) Figure 3.5-1 Configuration of Reset Flag Register (RSFR) Address bit7 bit6 bit5 bit4 000E H PONR ERST WDOG...
Page 62 CHAPTER 3 CPU Table 3.5-3 Explanation of Functions of Each Bit in the Reset Flag Register (RSFR) Bit name PONR: bit7 Power-on reset flag ERST: bit6 External reset flag bit WDOG: bit5 Watchdog reset flag SFTR: bit4 Software reset flag bit3 Unused bits bit0...
Page 63: External Reset Pin
3.5.2 External Reset Pin The external reset pin generates a reset by "L" level input. When an option setting for enabling reset output is selected, the "L" level signal is output depending on the internal reset source. ■ Block Diagram of External Reset Pin The external reset pin (RST) on models with supported reset output has hysteresis input and pull-up N-ch open drain output.
Page 64: Reset Operation
CHAPTER 3 CPU 3.5.3 Reset Operation The CPU reads the mode data (mode fetch) and reset vector from internal ROM according to the mode pin settings following the cancellation of a reset. For a return triggered by a reset when power is turned on and in stop mode, the CPU fetches the mode after oscillation stabilization wait time has expired.
Page 65: Mode Fetch
■ Mode Fetch The CPU reads the mode data and reset vector from internal ROM following the cancellation of the reset. ● Mode data (address: FFFD Set single-chip mode (00 ● Reset vector (address: FFFE Specify the address at which execution is to be started after the reset operation is completed. The CPU starts executing instructions from the specified address.
Page 66: State Of Each Pin At Reset
CHAPTER 3 CPU 3.5.4 State of Each Pin at Reset The state of each pin is initialized by a reset. ■ States of Pins during Reset When a reset occurs, most I/O pins (resource pins) become Hi-Z, and the CPU reads the mode data from internal ROM.
Page 67: Clock
Clock The clock generator includes the oscillation circuit. A high-speed clock is generated by connecting an external resonator for oscillation frequency. Alternatively, when the clock is supplied from an external source, a clock signal can be connected to the clock input pin.
Page 68 CHAPTER 3 CPU X0 pin Oscillation circuit frequency X1 pin Stop mode 1/4 frequency 1/8 frequency Oscillation control 1/16 frequency 1/64 frequency Sleep, stop, oscillation stabilization wait Stop : Oscillation frequency : Instruction cycle INST : Not affected by the gear. : The gear affects the operating speed or other settings.
Page 69: Clock Generator
3.6.1 Clock Generator The clock generator enables oscillation in active mode and disables oscillation in stop mode. ■ Clock Generator ● For a crystal resonator or ceramic resonator Connect it as shown in Figure 3.6-2 . Figure 3.6-2 Example of Connecting a Crystal Resonator or Ceramic Resonator ●...
Page 70: Clock Controller
CHAPTER 3 CPU 3.6.2 Clock Controller The clock controller consists of the following six blocks: • Oscillation circuit • System clock selector • Clock controller • Oscillation stabilization wait time selector • System clock control register (SYCC) • Standby control register (STBC) ■...
Page 71 ● Oscillator Oscillation circuit that halts oscillation in stop mode. ● System clock selector Selects one of four frequency-divided source clocks to be supplied to the clock control circuit. ● Clock controller Controls the operating clock supplied to the CPU and peripheral circuits according to the active (RUN) mode and standby mode (sleep, stop).
Page 72: System Clock Control Register (Sycc)
CHAPTER 3 CPU 3.6.3 System Clock Control Register (SYCC) The system clock control register (SYCC) manages clock settings such as selection of the clock speed and oscillation stabilization wait time. ■ Configuration of the System Clock Control Register (SYCC) Figure 3.6-5 Configuration of System Clock Control Register (SYCC) Address bit7 bit6...
Page 73 Table 3.6-1 Explanation of Functions of Each Bit in the System Clock Control Register (SYCC) Bit name SCM: System clock bit7 monitor bit bit6, Unused bits bit5 WT1, WT0: bit4, Oscillation bit3 stabilization wait time selection bits bit2 Unused bit CS1, CS0: bit1, Clock speed selection...
Page 74: Clock Mode
CHAPTER 3 CPU 3.6.4 Clock Mode The clock speed is switched by selecting one of four frequency-divided source clocks (gears). ■ Operations in Each Clock Mode Table 3.6-2 Operations in Each Clock Mode Clock speed Standby SYCC register mode (SYCC: CS1 and CS0) High speed...
Page 75: Operations In Active Mode
■ Operations in Active Mode In active (RUN) mode, the oscillator is generating a clock. The CPU, time-base timer, and other peripheral circuits operate using the clock. In active mode, all clock speeds except the time-base timer clock speed can be changed (using gears). In active mode, specifying standby mode results in a transition to sleep mode or stop mode.
Page 76: Oscillation Stabilization Wait Time
CHAPTER 3 CPU 3.6.5 Oscillation Stabilization Wait Time Oscillation stabilization wait time is to be applied when power is turned on to start the clock in RUN mode while the clock is stopped in stop mode. ■ Oscillation Stabilization Wait Time A ceramic or crystal resonator normally requires several or several tens of milli-seconds from oscillation start to oscillation stabilization at a specific cycle (oscillation frequency).
Page 77 ● Oscillation stabilization wait time at a reset Option settings specify oscillation stabilization wait time at a reset (initial values of WT1 and WT0). Cancellation of stop mode by external reset also applies oscillation stabilization wait time. Table 3.6-3 shows the relationship between the active mode operation start conditions and oscillation stabilization wait time.
Page 78: Standby Mode (Low-Power Consumption Mode)
CHAPTER 3 CPU Standby Mode (Low-Power Consumption Mode) The MB89202/F202RA series supports sleep mode and stop mode in standby mode. Transition to standby mode is controlled by the standby control register (STBC) settings. In active mode, transition to sleep mode or stop mode is allowed. In standby mode, operation of the CPU and peripheral functions is stopped to reduce power consumption.
Page 79: Operations In Standby Mode
3.7.1 Operations in Standby Mode This section describes CPU and peripheral function operation in standby mode. ■ Operations in Standby Mode Table 3.7-1 Operations of the CPU and Peripheral Functions in Standby Mode Function Clock Instruction I/O port Time-base timer Watchdog timer 8-bit PWM timer/counter 8/16-bit capture timer/counter...
Page 80: Sleep Mode
CHAPTER 3 CPU 3.7.2 Sleep Mode This section describes sleep mode. ■ Operations Relating to Sleep Mode ● Transition to sleep mode In sleep mode, the operating clock for CPU is stopped. Although the CPU stops storing data in the registers and RAM used immediately before transition to sleep mode, peripheral functions, excepting the watchdog timer, continue to operate.
Page 81: Stop Mode
3.7.3 Stop Mode This section describes the stop mode. ■ Operations Relating to Stop Mode ● Transition to stop mode In stop mode, the oscillation frequency is stopped. Most functions stop storing data in the registers and RAM used immediately before transition to stop mode. The clock circuit stops oscillating, the peripheral functions and CPU stop operating, but the external interrupt circuit continues to operate.
Page 82: Standby Control Register (Stbc)
CHAPTER 3 CPU 3.7.4 Standby Control Register (STBC) The standby control register (STBC) controls transition to sleep /stop modes, pin state settings in stop mode, and software reset. ■ Standby Control Register (STBC) Figure 3.7-1 Standby Control Register (STBC) Address bit7 bit6 bit5...
Page 83 Table 3.7-2 Explanation of Functions of Each Bit in the Standby Control Register (STBC) Bit name STP: bit7 Stop bit SLP: bit6 Sleep bit SPL: bit5 pin state setting bit RST: bit4 Software reset bit RESV: bit3 Reserved bit bit2 to bit0 Unused bits Description This bit specifies transition to stop mode.
Page 84: Diagram For State Transition In Standby Mode
CHAPTER 3 CPU 3.7.5 Diagram for State Transition in Standby Mode Figure 3.7-2 shows the state transition diagram in standby mode. ■ Diagram for State Transition in Standby Mode Power turned on Power-on reset Oscillation stabilization wait reset mode (10) Oscillation stabilization wait : Cancellation of reset input...
Page 85 ● Transition to and cancellation of clock mode (non-standby mode) Table 3.7-3 Transition to and Cancellation of Clock Mode State transition Transition to active mode after power-on reset Reset in RUN mode ● Transition to and cancellation of standby mode Table 3.7-4 Transition to and Cancellation of Standby Mode State transition Transition to sleep mode...
Page 86: Notes On Standby Mode
CHAPTER 3 CPU 3.7.6 Notes on Standby Mode Even if the standby control register (STBC) sets standby mode, transition to standby mode is not allowed when a peripheral function generates an interrupt request. When an interrupt causes a return from standby mode to active mode, subsequent operations depend on whether interrupt requests are acceptable.
Page 87 CHAPTER 3 CPU ■ Oscillation Stabilization Wait Time The oscillator for oscillation frequency stops in stop mode, thus oscillation stabilization wait time must be applied after the oscillator is activated. Use one of three clock oscillation stabilization wait time settings generated by the time-base timer. If the interval selected for the time-base timer is shorter than the oscillation stabilization wait time, an interval timer interrupt request is generated during oscillation stabilization wait time.
Page 88: Memory Access Mode
CHAPTER 3 CPU Memory Access Mode The MB89202/F202RA series supports only single-chip mode for access to memory. ■ Single-chip Mode In single-chip mode, only internal RAM and ROM are used. The CPU can access only the internal I/O area, RAM area, and ROM area. ■...
Page 89 Figure 3.8-2 Operations for Selecting Memory Access Wait for cancellation of the reset source (external reset or oscillation stabilization wait time) Mode fetch Check of the mode data Prohibited Setup of I/O pin functions at execution of program (RUN mode) Source of a reset is generated.
Page 90 CHAPTER 3 CPU...
Page 91: Chapter 4 I/O Ports
CHAPTER 4 I/O PORTS This chapter describes the functions and operations of I/O ports. 4.1 Overview of I/O Ports 4.2 Port 0 4.3 Port 3 4.4 Port 4 4.5 Port 5 4.6 Port 6 4.7 Port 7 4.8 Programming Example of I/O Port...
Page 92: Overview Of I/O Ports
CHAPTER 4 I/O PORTS Overview of I/O Ports Six I/O ports (comprising 26 pins) are available as general-purpose I/O ports (parallel I/O ports). These ports also serve peripherals (as I/O pins for specific peripheral functions). ■ Functions of I/O Ports The I/O ports function to output data from the CPU to I/O pins via their port data register (PDR) and send signals input to I/O pins to the CPU.
Page 93 Table 4.1-2 Registers of Ports Register name Port 0 data register Port 0 data direction register Port 0 pull-up setting register Port 3 data register Port 3 data direction register Port 3 pull-up setting register Port 4 data register Port 4 data direction register Port 4 output form setting register Port 5 data register Port 5 data direction register...
Page 94: Port 0
CHAPTER 4 I/O PORTS Port 0 Port 0 is a general-purpose I/O port and may also serve as peripheral inputs. The pins of this port can be used for peripherals or normal port function that can be selected according to the setting of a bit corresponding to the pin on a specific register. This section mainly explains the general-purpose I/O function of the port.
Page 95 ■ Block Diagram of Port 0 PDR read PDR read (when read-modify-write is performed) PDR write DDR write PUL read PUL write SPL: Pin status setting bit of standby control register (STBC) Note: When the A/D converter is used, deselect pull-up action for pins P03/INT23/AN7 to P00/INT20/AN4. Pins set to be used as analog input pins must not be used as an output port.
Page 96: Registers Of Port 0 (Pdr0, Ddr0, And Pul0)
CHAPTER 4 I/O PORTS 4.2.1 Registers of Port 0 (PDR0, DDR0, and PUL0) This section describes the registers associated with port 0. ■ Functions of Port 0 Registers ● Port 0 data register (PDR0) The PDR0 register indicates the state of the output latch. For a pin set to function as an output port, the same value ("0"...
Page 97 Table 4.2-3 lists the functions of the port 0 registers. Table 4.2-3 Functions of Port 0 Registers Register When being Data name read Pin state is "L" level. Port 0 data register (PDR0) Pin state is "H" level. Port 0 data Read direction prohibited...
Page 98: Operations Of Port 0 Functions
CHAPTER 4 I/O PORTS 4.2.2 Operations of Port 0 Functions This section describes the operation of port 0. ■ Operation of Port 0 ● Operation in output port mode When "1" is written to a bit of the DDR0 register, the bit corresponding to a pin of port 0, the pin functions as an output port.
Page 99 ● Operation in stop mode When the pin state setting bit of the standby control register (STBC: SPL) is "1" and when the stop mode is entered, the output transistor is turned OFF and the pin becomes Hi-Z because the output transistor is forcibly turned OFF without respect to the value existing on the DDR0 register in the bit position corresponding to the pin.
Page 100: Port 3
CHAPTER 4 I/O PORTS Port 3 Port 3 is a general-purpose I/O port and may also serve as input pins for external interrupts as well as input and output pins for peripherals. This section mainly explains the general-purpose I/O function of the port. This section also describes port 3 concerning to the structure, pins, a block diagram of pins, and associated registers.
Page 101 ■ Block Diagram of Port 3 PDR read PDR read (when read-modify-write is performed) PDR write DDR write PUL read PUL write Note: Because the value states of the pins are always input to the external interrupt circuit, when a pin is used as a normal I/O port, the operation of the external interrupt circuit corresponding to the pin must be inhibited.
Page 102: Registers Of Port 3 (Pdr3, Ddr3, Pul3)
CHAPTER 4 I/O PORTS 4.3.1 Registers of Port 3 (PDR3, DDR3, PUL3) This section describes the registers associated with port 3. ■ Functions of Port 3 Registers ● Port 3 data register (PDR3) The PDR3 register indicates the state of the pins. For a pin set to function as an output port, the same value ("0"...
Page 103 Table 4.3-3 lists the functions of port 3 registers. Table 4.3-3 Functions of Port 3 Registers Register When being Data name read Pin state is "L" level. Port 3 data register (PDR3) Pin state is "H" level. Port 3 data Read direction prohibited...
Page 104: Operations Of Port 3 Functions
CHAPTER 4 I/O PORTS 4.3.2 Operations of Port 3 Functions This section describes the operation of port 3. ■ Operation of Port 3 ● Operation in output port mode When "1" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, the pin functions as an output port.
Page 105 ● Operation when a reset is performed When the CPU is reset, the bits of the DDR3 register are initialized to "0", at which time the output transistors become OFF (input port mode) and the pins become Hi-Z. However, CPU resets do not initialize the PDR3 register. If a pin is used as an output port after the reset, reinitialize the PDR3 register to contain new output data in the bit position corresponding to the pin and then set the corresponding bit of the DDR3 register so that the pin will function as an output port.
Page 106: Port 4
CHAPTER 4 I/O PORTS Port 4 Port 4 is a type of I/O port that is switched between CMOS push-pull and N-ch open- drain and may also serve analog inputs. Each pin of this port can be used for peripherals or normal port function that can be selected according to the setting of the bit corresponding to the pin on a specific register.
Page 107: Block Diagram Of Port 4
■ Block Diagram of Port 4 PDR read PDR read (when read-modify-write is performed) Output latch PDR write DDR write DDR read OUT read OUT write ■ Registers of Port 4 The registers PDR4, DDR4, and OUT4 are associated with port 4. The bits of these registers correspond to the pins of port 4 in one-to-one correspondence.
Page 108: Registers Of Port 4 (Pdr4)
CHAPTER 4 I/O PORTS 4.4.1 Registers of Port 4 (PDR4) This section describes the registers associated with port 4. ■ Functions of Port 4 Registers ● Port 4 data register (PDR4) The PDR4 register indicates the state of the pins. For a pin set to function as an output port, the same value ("0"or "1") as held by the output latch can be read from this register.
Page 109: Operations Of Port 4 Functions
4.4.2 Operations of Port 4 Functions This section describes the operation of port 4. ■ Operation of Port 4 ● Operation in output port mode When "1" is written for a bit of the DDR4 register, the bit corresponding to a pin of port 4, the pin functions as an output port.
Page 110: Port 5
CHAPTER 4 I/O PORTS Port 5 Port 5 is a general-purpose I/O port and may also serve the input/output for peripherals. The pins of this port can be used for peripherals or normal port function that can be selected according to the setting of the bit corresponding to the pin on a specific register.
Page 111: Block Diagram Of Port 5
■ Block Diagram of Port 5 PDR read PDR read (when read-modify-write is performed) Output latch PDR write DDR write DDR read PUL read PUL write ■ Registers of Port 5 The registers PDR5, DDR5, and PUL5 are associated with port 5. One of the bits of these registers corresponds to one pin of port 5.
Page 112: Registers Of Port 5 (Pdr5, Ddr5, Pul5)
CHAPTER 4 I/O PORTS 4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5) This section describes the registers associated with port 5. ■ Functions of Port 5 Registers ● Port 5 data register (PDR5) The PDR5 register indicates the state of pins. For a pin set to function as an output port, the same value ("0"...
Page 113 Table 4.5-3 Functions of Port 5 Registers Register When being Data name read Pin state is "L" level. Port 5 data register (PDR5) Pin state is "H" level. Input port pin Port 5 data direction register (DDR5) Output port pin R/W : Readable/Writable : Undefined ●...
Page 114: Operations Of Port 5 Functions
CHAPTER 4 I/O PORTS 4.5.2 Operations of Port 5 Functions This section describes the operation of port 5. ■ Operation of Port 5 ● Operation in output port mode When "1" is written for a bit of the DDR5 register, the bit corresponding to the pin of port 5, the pin functions as an output port.
Page 115 Table 4.5-4 summarizes the operating modes of the pin of port 5. Table 4.5-4 Operating Modes of Pin of Port 5 Pin name Normal operation, sleep, stop (SPL = 0) P50/PWM General-purpose I/O port further may serve I/O for peripherals SPL : Pin state setting bit of standby control register (STBC: SPL) Hi-Z: High impedance Note:...
Page 116: Port 6
CHAPTER 4 I/O PORTS Port 6 Port 6 is a general-purpose I/O port. This section describes the port function when operating as general-purpose I/O port. This section also describes the structure, pins, the block diagram of pins, and associated registers of port 6. ■...
Page 117 ■ Block Diagram of Port 6 PDR read PDR read (when read-modify-write is performed) PDR write DDR write DDR read PUL read PUL write PDR read PDR read (when read-modify-write is performed) PDR write DDR read DDR read PUL read PUL write Figure 4.6-1 Block Diagram of Port6 For MB89202/V201...
Page 118 CHAPTER 4 I/O PORTS ■ Registers PDR6, DDR6, and PUL6 of Port 6 Registers PDR6, DDR6, and PUL6 are associated with port 6. The bits of these registers correspond to the pins of port 6 in one-to-one correspondence. Table 4.6-2 tabulates the correspondence between the pins and the bits of the port 6 registers. Table 4.6-2 Correspondence between the Pins and the Bits of Port 6 Registers Port name PDR6, DDR6, PUL6...
Page 119: Registers Of Port 6 (Pdr6, Ddr6, Pul6)
4.6.1 Registers of Port 6 (PDR6, DDR6, PUL6) This section describes the registers associated with port 6. ■ Functions of Port 6 Registers ● Port 6 data register The PDR6 register indicates the state of the output latch. For a pin set to function as an output port, the same value ("0"...
Page 120 CHAPTER 4 I/O PORTS ● Port 6 pull-up setting register (PUL6) The bits of the pull-up setting register correspond to the pins of port 6 in one-to-one correspondence. When the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level (pull-up state) instead of Hi-Z during stop (SPL = 1).
Page 121: Operations Of Port 6 Functions
4.6.2 Operations of Port 6 Functions This section describes the operation of port 6. ■ Operation of Port 6 ● Operation in output port mode When "1" is written for a bit of the DDR6 register, the bit corresponding to a pin of port 6, the pin functions as an output port.
Page 122 CHAPTER 4 I/O PORTS Table 4.6-4 Operating Modes of Pins of Port 6 Pin name Normal operation, sleep, stop (SPL = 0) P60, P61 General-purpose I/O port Note: When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level instead of Hi-Z in stop mode (SPL = 1).
Page 123: Port 7
Port 7 Port 7 is a general-purpose I/O port. This section describes the port function when operating as general-purpose I/O port. This section also describes the port structure, pins, the pin block diagram associated registers of port 7. ■ Structure of Port 7 Port 7 comprises the following four elements: •...
Page 124: Block Diagram Of Port 7
CHAPTER 4 I/O PORTS ■ Block Diagram of Port 7 PDR read PDR read (when read-modify-write is performed) PDR write DDR write DDR read PUL read PUL write ■ Registers PDR7, DDR7, and PUL7 of Port 7 Registers PDR7, DDR7, and PUL7 are associated with port 7. The bits of these registers correspond to the pins of port 7 in one-to-one correspondence.
Page 125: Registers Of Port 7 (Pdr7, Ddr7, Pul7)
4.7.1 Registers of Port 7 (PDR7, DDR7, PUL7) This section describes the registers associated with port 7. ■ Functions of Port 7 Registers ● Port 7 data register (PDR7) The PDR7 register indicates the state of the output latch. For a pin set to function as an output port, the same value ("0"...
Page 126 CHAPTER 4 I/O PORTS ● Port 7 pull-up setting register (PUL7) The bits of the pull-up setting register correspond to the pins of port 7 in one-to-one correspondence. When the pull-up resistor is selected by using the pull-up setting register, the pin will be at "H" level (pull-up state) instead of Hi-Z during stop (SPL = 1).
Page 127: Operations Of Port 7 Functions
4.7.2 Operations of Port 7 Functions This section describes the operation of port 7. ■ Operation of Port 7 ● Operation in output port mode When "1" is written for a bit of the DDR7 register, the bit corresponding to a pin of port 7, the pin functions as an output port.
Page 128 CHAPTER 4 I/O PORTS Table 4.7-4 summarizes the operating modes of the pins of port 7. Table 4.7-4 Operating Modes of Pins of Port 7 Pin name Normal operation, sleep, stop (SPL = 0) P70 to P72 General-purpose I/O port Note: When the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H"...
Page 129: Programming Example Of I/O Port
Programming Example of I/O Port This section provides an example of programming with I/O ports. ■ I/O Port Programming Example ● Processing specification Ports 0 and 3 are used to light all seven segments of LED (eight segments if the decimal point is included). Pin P00 is connected to the anode common pin of LED and pins P30 to P37 are connected to the pins of the segments.
Page 130 CHAPTER 4 I/O PORTS ● Coding example PDR0 EQU 0000H DDR0 EQU 0001H PDR3 EQU 000CH DDR3 EQU 000DH ;------------------------------Main program----------------------------------------------------------------------- CSEG CLRB PDR0:0 MOV PDR3,#11111111B MOV DDR0,#11111111B MOV DDR3,#11111111B ENDS ;--------------------------------------------------------------------------------------------------------------------- ; Address of port 0 data register ; Address of port 0 data direction register ;...
Page 131: Chapter 5 Time-Base Timer
CHAPTER 5 TIME-BASE TIMER This chapter describes the functions and operations of the time-base timer. 5.1 Overview of Time-base Timer 5.2 Configuration of Time-base Timer 5.3 Time-base Timer Control Register (TBTC) 5.4 Interrupt of Time-base Timer 5.5 Operations of Time-base Timer Functions 5.6 Notes on Using Time-base Timer 5.7 Program Example for Time-base Timer...
Page 132: Overview Of Time-Base Timer
CHAPTER 5 TIME-BASE TIMER Overview of Time-base Timer The time-base timer functions as an interval timer. The time-base timer is a 21-bit free- run counter that counts up in synchronization with the internal count clock (at the oscillation frequency divided by 2). The timer also has an interval timer function to select one of four time intervals.
Page 133 Table 5.1-2 Clock Cycles Supplied by Time-base Timer (2/2) Clock supplied to Watchdog timer A/D converter : Oscillation frequency The values enclosed in parentheses are time intervals when the oscillation frequency is 12.5 MHz. Note: Because oscillation cycles vary immediately after oscillation starts, the oscillation stabilization wait time is listed for reference.
Page 134: Configuration Of Time-Base Timer
CHAPTER 5 TIME-BASE TIMER Configuration of Time-base Timer The time-base timer consists of the following four function blocks. • Time-base counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of Time-base Timer Figure 5.2-1 Block Diagram of Time-base Timer Time-base timer counter divided...
Page 135: Time-Base Timer Control Register (Tbtc)
Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) selects a time interval, clears the counter, controls interrupts, or checks the status. ■ Time-base Timer Control Register (TBTC) Figure 5.3-1 Time-base Timer Control Register (TBTC) Address bit7 bit6 bit5 000A TBOF TBIE R/W R/W...
Page 136 CHAPTER 5 TIME-BASE TIMER Table 5.3-1 Explanation of Functions of Each Bit in Time-base Timer Control Register (TBTC) Bit name TBOF: bit7 Overflow interrupt request flag bit TBIE: bit6 Interrupt request enable bit bit5 Unused bits bit3 bit2, TBC1, TBC0: bit1 Time interval selection bits TBR:...
Page 137: Interrupt Of Time-Base Timer
Interrupt of Time-base Timer The time-base timer counter generates an interrupt when the specified bit of the counter overflows (interval timer function). ■ Interrupts when the Interval Timer Function is Enabled The counter counts up with the internal count clock. When the specified interval timer bit overflows, the overflow interrupt request flag bit (TBTC: TBOF) is set to "1".
Page 138: Operations Of Time-Base Timer Functions
CHAPTER 5 TIME-BASE TIMER Operations of Time-base Timer Functions The time-base timer functions as an interval timer or supplies clocks to some peripherals. ■ Operations of Interval Timer Function (Time-base Timer) To use as an interval timer, the settings shown below must be made. TBOF TBIE TBTC : Used bit...
Page 139 Figure 5.5-2 Operations of Time-base Timer Counter value 1FFFFF Oscillation stabilization overflow 000000 operation start Power-on reset (optional) Cleared by interrupt handling routine TBOF bit TBIE bit SLP bit (STBC register) STP bit (STBC register) Note: When the interval time selection bits of time-base timer control register (TBTC : TBC1, TBC0) are set to 11 (2 : Oscillation stabilization time Cleared by switching to stop mode...
Page 140: Notes On Using Time-Base Timer
CHAPTER 5 TIME-BASE TIMER Notes on Using Time-base Timer Notes on using the time-base timer are shown below. ■ Notes on Using Time-base Timer ● Notes on using programs to set time-base timer When the interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit is enabled (TBTC: TBIE = 1), a return from interrupt handling is not possible.
Page 141: Program Example For Time-Base Timer
Program Example for Time-base Timer Programming examples for the time-base timer are shown below. ■ Programming Examples for Time-base Timer ● Processing specification Repeatedly generate an interval timer interrupt at intervals of 2 time interval is approximately 21.0 ms (operating at 12.5 MHz). ●...
Page 142 CHAPTER 5 TIME-BASE TIMER POPW RETI ENDS ; --------------------------------------------------------------------------------------------------------------------...
Page 143: Chapter 6 Watchdog Timer
CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. 6.1 Overview of Watchdog Timer 6.2 Configuration of Watchdog Timer 6.3 Watchdog Control Register (WDTC) 6.4 Operations of Watchdog Timer Functions 6.5 Notes on Using Watchdog Timer 6.6 Program Example for Watchdog Timer...
Page 144: Overview Of Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Overview of Watchdog Timer The watchdog timer is a 1-bit counter that uses output from the time-base timer, based on oscillation frequency, as the count clock. The watchdog timer resets the CPU when not cleared within a specified period after activation. ■...
Page 145: Configuration Of Watchdog Timer
Configuration of Watchdog Timer The watchdog timer consists of the following four function blocks. • Watchdog timer counter • Reset control circuit • Counter clear control circuit • Watchdog control register (WDTC) ■ Block Diagram of Watchdog Timer Figure 6.2-1 Block Diagram of Watchdog Timer Watchdog control register (WDTC) (Time- base timer...
Page 146: Watchdog Control Register (Wdtc)
CHAPTER 6 WATCHDOG TIMER Watchdog Control Register (WDTC) The watchdog control register (WDTC) activates and clears the watchdog timer. ■ Watchdog Control Register (WDTC) Figure 6.3-1 Watchdog Control Register (WDTC) Address bit7 bit6 bit5 0009 RESV : Readable/writable : Unused : Undefined Table 6.3-1 Explanation of Functions of Each Bit in Watchdog Control Register (WDTC) Bit name...
Page 147: Operations Of Watchdog Timer Functions
Operations of Watchdog Timer Functions The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. ■ Operations of Watchdog Timer ● Activating watchdog timer The watchdog timer is activated when the first time "0101 (WDTC: WTE3 to WTE0) of the watchdog control register. The watchdog timer cannot be stopped without accepting a reset upon activation.
Page 148: Notes On Using Watchdog Timer
CHAPTER 6 WATCHDOG TIMER Notes on Using Watchdog Timer Notes on using the watchdog timer are provided below. ■ Notes on Using Watchdog Timer ● Stopping watchdog timer The watchdog timer cannot be stopped without accepting a reset upon activation. ●...
Page 149: Program Example For Watchdog Timer
Program Example for Watchdog Timer Programming examples for the watchdog timer are provided below. ■ Programming Examples of Watchdog Timer ● Processing specification • Activate the watchdog timer immediately after the program starts. • Clear the watchdog timer whenever the loop of the main program is run. •...
Page 150 CHAPTER 6 WATCHDOG TIMER...
Page 151: 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER This chapter describes the functions and operations of 8-bit PWM timer. 7.1 Overview of 8-bit PWM Timer 7.2 Configuration of 8-bit PWM Timer 7.3 Pin of 8-bit PWM Timer 7.4 Registers of 8-bit PWM Timer 7.5 Interrupt of 8-bit PWM Timer 7.6 Operations of the Interval Timer Functions 7.7 Operations of the 8-bit PWM Timer Functions...
Page 152: Overview Of 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Overview of 8-bit PWM Timer An 8-bit PWM timer has the interval timer functions and the PWM timer functions of an 8-bit resolution. A counter is incremented using interval timer functions in synchronization with three types of internal count clocks or the output of 8/16-bit capture timer/counter.
Page 153: Pwm Timer Functions
Note: Calculation example of intervals and square wave frequency The following expression is the interval when the count clock cycle is set to 1 t oscillation frequency (F are set. Another expression is the frequency of the square wave output from the PWM pin that is operated continuously without changing the COMR register value.
Page 154 CHAPTER 7 8-BIT PWM TIMER Figure 7.1-1 Configuration Example of the D/A Converter with the PWM Output and a Low-Pass Filter PWM pin Analog output waveform PWM output waveform Note: While PWM timer functions are enabled, no interrupt request occurs. PWM output Relationship between analog output voltage and PWM output waveform...
Page 155: Configuration Of 8-Bit Pwm Timer
Configuration of 8-bit PWM Timer An 8-bit PWM timer consists of the following six blocks. • Count clock selector • 8-bit counter • Comparator • PWM generation and output control circuit • PWM compare register (COMR) • PWM control register (CNTR) ■...
Page 156 CHAPTER 7 8-BIT PWM TIMER ● Count clock selector The count clock selector selects one of three types of internal counter clock. The selector also selects an 8/ 16-bit capture timer or counter and uses it to increment the count of the 8-bit counter. ●...
Page 157: Pin Of 8-Bit Pwm Timer
Pin of 8-bit PWM Timer This section describes the pin and provides a block diagram of the pin related to the 8- bit PWM timer. ■ Pin Related to the 8-bit PWM Timer The pin related to the 8-bit PWM timer is the P50/PWM pin. ●...
Page 158: Registers Of 8-Bit Pwm Timer
CHAPTER 7 8-BIT PWM TIMER Registers of 8-bit PWM Timer This section describes the registers related to the 8-bit PWM timer. ■ Registers Related to the 8-bit PWM Timer Figure 7.4-1 Registers Related to the 8-bit PWM Timer CNTR (PWM control register) Address bit7 bit6...
Page 159: Pwm Control Register (Cntr)
7.4.1 PWM Control Register (CNTR) The PWM control register (CNTR) is used to select the operation mode (interval timer operation or PWM timer operation) of the 8-bit PWM timer, switch the resolution of the PWM timer functions, and select the count clock. ■...
Page 160 CHAPTER 7 8-BIT PWM TIMER Table 7.4-1 Explanation of the Functions of Each Bit in the PWM Control Register (CNTR) Bit name P/TX: bit7 Bit to select the operation mode bit6 Unused bit bit5, P1, P0: bit4 Bits to select the clock TPE: bit3 Bit to enable the counter...
Page 161: Pwm Compare Register (Comr)
7.4.2 PWM Compare Register (COMR) The PWM compare register (COMR) is used to set an interval while the internal timer functions are enabled. In addition, the register becomes the "H" level width of a pulse while the PWM timer functions are enabled. ■...
Page 162 CHAPTER 7 8-BIT PWM TIMER ● While the PWM timer is operating: Specify the "H" level width of a pulse in the register to which the value that is compared with the counter value is to be set. Until the settings written to this register match the counter value, "H" is output from the PWM pin. When a match is found, "L"...
Page 163: Interrupt Of 8-Bit Pwm Timer
Interrupt of 8-bit PWM Timer An interrupt factor of an 8-bit PWM timer can be a match between the counter value and the PWM compare register value while interval timer functions are operating. While the PWM timer functions are enabled, an interrupt request does not occur. ■...
Page 164: Operations Of The Interval Timer Functions
CHAPTER 7 8-BIT PWM TIMER Operations of the Interval Timer Functions This section describes the operations of the interval timer functions of an 8-bit PWM timer. ■ Operations of the Interval Timer Functions To make an 8-bit PWM timer operate as an interval timer, set registers as shown in Figure 7.6-1 . Figure 7.6-1 Setting Interval Timer Functions bit7 CNTR...
Page 165 Figure 7.6-2 Operations of an 8-bit PWM Timer Comparison value Counter value Timer cycle COMR value TIR bit TPE bit OE bit PWM pin When the bit to control the output pin (OE) is "0", the pin functions as a general-purpose I/O port pin (P50).
Page 166: Operations Of The 8-Bit Pwm Timer Functions
CHAPTER 7 8-BIT PWM TIMER Operations of the 8-bit PWM Timer Functions This section describes the operations of the 8-bit PWM timer functions. ■ Operations of the 8-bit PWM Timer Functions To enable 8-bit PWM timer functions, set registers as shown in Figure 7.7-1 . Figure 7.7-1 Setting 8-bit PWM Timer Functions bit7 P/TX...
Page 167 Figure 7.7-2 Output Example of the PWM Waveform of 8-bit PWM Timer Functions When the COMR Register Value is 00 Counter value "H" PWM waveform "L" When the COMR register value is 80 Counter value "H" PWM waveform "L" When the COMR register value is FF Counter value "H"...
Page 168: States In Each Mode During Operation
CHAPTER 7 8-BIT PWM TIMER States in Each Mode During Operation This section describes the operations for a move to the sleep mode, a move to the stop mode, and the occurrence of a suspend request during the operation of an 8-bit PWM timer.
Page 169 ● While interval timer functions are enabled: Figure 7.8-1 Operation of the Counter in the Standby Mode and during Suspension (while Interval Counter value COMR value (FF Timer cycle TIR bit TPE bit PWM pin (OE = 1) SLP bit (STBC register) STP bit...
Page 170 CHAPTER 7 8-BIT PWM TIMER ● While PWM timer functions are enabled: Figure 7.8-2 Operation in the Standby Mode and during Suspension (while PWM Timer Functions are PWM pin (PWM waveform) TPE bit SLP bit (STBC register) STP bit (STBC register) *: When the bit to specify the pin state (STBC: SPL) of the standby control register is "1", and the PWM pin is not pulled up, the PWM pin in the stop mode is Hi-Z.
Page 171: Notes On Using 8-Bit Pwm Timer
Notes on Using 8-bit PWM Timer This section provides notes on using 8-bit PWM timer. ■ Notes on Using 8-bit PWM Timer ● Error The activation of the counter by a program does not synchronize the start of an increment by the selected count clock.
Page 172 CHAPTER 7 8-BIT PWM TIMER MOV CNTR, #11001010B ; Starts PWM operations, internal clocks, and count operations. "H" Depending on the port state "L" (2) When OE is set after TPE and P/TX are set: MOV CNTR, #11001000B ; Starts PWM operations, internal clocks, and count operations. Check MOV CNTR, #11001010B ;...
Page 173: Program Example For Pwm Timer
7.10 Program Example for PWM Timer This section describes program examples of an 8-bit PWM timer. ■ Program Example of Interval Timer Functions ● Processing specifications • 5 ms interval timer interrupts occur repeatedly. • The square waveform that inverts at an interval is output to the P50/PWM pin. •...
Page 174 CHAPTER 7 8-BIT PWM TIMER User processing POPW XCHW POPW RETI ENDS ; -------------------------------------------------------------------------------------------------------------------- ; Restoring A and T...
Page 175: Program Example Of Pwm Timer Functions
■ Program Example of PWM Timer Functions ● Processing specifications • A PWM wave with a duty ratio of 50% is generated. The duty ratio is then changed to 25%. • No interrupt occurs. • When the count clock is 16 t MHz ×...
Page 176 CHAPTER 7 8-BIT PWM TIMER...
Page 177: 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/ COUNTER This chapter describes the functions and operation of the 8/16-bit capture timer/counter. 8.1 Overview of 8/16-bit Capture Timer/Counter 8.2 Configuration of 8/16-bit Capture Timer/Counter 8.3 Pins of 8/16-bit Capture Timer/Counter 8.4 Registers of 8/16-bit Capture Timer/Counter 8.5 8/16-bit Capture Timer/Counter of Interrupts 8.6 Explanation of Operations of Interval Timer Functions 8.7 Operation of Counter Functions...
Page 178: Overview Of 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Overview of 8/16-bit Capture Timer/Counter The 8/16-bit capture timer/counter consists of two 8-bit counters (timer 0 and timer 1). These counters can be used separately (8-bit mode) or in combination (16-bit mode). Timer 0 provides seven internal count clocks. This timer can select the interval timer function or counter function.
Page 179 Table 8.1-1 to Table 8.1-3 show the interval time and square wave output range in each operation mode. Table 8.1-1 Timer 0 Interval Time and Square Wave Output Range in 8-bit Mode Count clock cycle INST INST INST Internal count clock INST 128t INST...
Page 180 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Table 8.1-3 Interval Time and Square Wave Output Range in 16-bit Mode Count clock cycle INST INST INST Internal count clock INST 128t INST 256t INST 512t INST External clock : Instruction cycle (this cycle is affected by the clock mode, etc.) INST : External clock cycle (1t Note:...
Page 181 ■ Counter Function The counter function counts the falling edges of the external clocks input to the P33/EC external pin. The 8/ 16-bit capture timer/counter can operate independently because the EC pin acts as an external clock input pin. Only timer 0 can select the external clock. The counter function operates using timer 0 with the 8-bit mode or with the 16-bit mode.
Page 182: Configuration Of 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Configuration of 8/16-bit Capture Timer/Counter The 8/16-bit capture timer/counter consists of the following seven blocks: • Count clock selectors 0/1 • Counter circuits 0/1 • Square wave output control circuit • Timer 0/1 data registers (TDR0, TDR1) •...
Page 183 ● Count clock selectors 0/1 Circuits that select input clocks. In timer 0 for the 8-bit mode or in the 16-bit mode, count clock selector 0/ 1 can select seven internal clocks and one external clock. In timer 1 for the 8-bit mode, the selector can select only seven internal clocks.
Page 184: Pins Of 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Pins of 8/16-bit Capture Timer/Counter This section provides pins of 8/16-bit capture timer/counter and a block diagram for these pins. ■ Pins of 8/16-bit Capture Timer/Counter 8/16-bit capture timer/counter pins include P33/EC and P34/TO/INT10. ● P33/EC pin The P33/EC pin shares functions of the general-purpose I/O port (P33) and the external clock for the timer or capture input pin (EC).
Page 185 ■ Block Diagram for 8/16-bit Capture Timer/Counter Pins Figure 8.3-1 Block Diagram for 8/16-bit Capture Timer/Counter Pins PDR read PDR read (At read-modify-write) Output latch PDR write DDR write PUL read PUL write Note: When "pull-up resistor available" is selected in the pull-up setting register, the pin state in the stop mode (SPL = 1) becomes high (pull-up state), not Hi-Z.
Page 186: Registers Of 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Registers of 8/16-bit Capture Timer/Counter This section shows registers of 8/16-bit capture timer/counter. ■ Registers of 8/16-bit Capture Timer/Counter Figure 8.4-1 Registers of 8/16-bit Capture Timer/Counter TCCR (capture control register) Address bit7 0019 CPIF TCR1 (timer 1 control register) Address bit7 001A...
Page 187: Capture Control Register (Tccr)
8.4.1 Capture Control Register (TCCR) The capture control register (TCCR) is used to select functions and detection edges, control interrupts, and check interrupt states in timer 0 for the 8-bit mode of the 8/16 bit capture timer/counter or in capture mode (16-bit mode). ■...
Page 188 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Table 8.4-1 Explanation of Functions of Each Bit in Capture Control Register (TCCR) Bit name CPIF: bit7 Capture edge detection flag bit CFCLR: bit6 Capture edge detection flag clear bit CPIEN: bit5 Capture interrupt request enable bit CCMSK: bit4...
Page 189: Timer 0 Control Register (Tcr0)
8.4.2 Timer 0 Control Register (TCR0) The timer 0 control register (TCR0) is used to select functions, allow and prohibit operation, control interrupts, and check interrupt states in timer 0 for the 8-bit mode of the 8/16-bit capture timer/counter or in the 16-bit mode. Even if only timer 0 is used in the 8-bit mode, the timer 1 control register (TCR1) must be initialized.
Page 190 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Table 8.4-2 Explanation of Functions of Each Bit in Timer 0 Control Register (TCR0) Bit name TIF0: bit7 Compare match detection flag bit TFCR0: bit6 Compare match detection flag clear bit T0IEN: bit5 Interrupt request enable CINV: bit4 Count clock selection bit...
Page 191: Timer 1 Control Register (Tcr1)
8.4.3 Timer 1 Control Register (TCR1) The timer 1 control register (TCR1) is used to select functions, allow and prohibit operation, control interrupts, and check interrupt states in timer 1 for the 8-bit mode of the 8/16-bit capture timer/counter. When used in the 16-bit mode, TCR1 is controlled by the timer 0 control register (TCR0), but TCR1 setting is required.
Page 192 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Table 8.4-3 Explanation of Functions of Each Bit in Timer 1 Control Register (TCR1) Bit name TIF1: bit7 Compare match detection flag bit TFCR1: bit6 Compare match detection flag clear bit T1IEN: bit5 Interrupt request enable bit4 Not used bit3...
Page 193: Timer Output Control Register (Tcr2)
8.4.4 Timer Output Control Register (TCR2) The timer output control register (TCR2) is used to allow and prohibit the square wave output of the 8/16-bit capture timer/counter and select timer 0 output and timer 1 output. ■ Timer Output Control Register (TCR2) Figure 8.4-5 Timer Output Control Register (TCR2) Address bit7...
Page 194: Timer 0 Data Register (Tdr0)
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER 8.4.5 Timer 0 Data Register (TDR0) The timer 0 data register (TDR0) is used to set the timer 0 value in the 8-bit mode of the 8/16-bit capture timer/counter or the interval timer value (interval timer function) or counter value (counter function) of the lower 8 bits in 16-bit mode.
Page 195 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ● 16-bit mode The values in TDR0 are compared with the counter values in the lower 8 bits of the 16-bit timer. When the interval timer function is used, the lower 8 bits of the interval time are set. When the counter function is used, the lower 8 bits of the count value to be detected are set.
Page 196: Timer 1 Data Register (Tdr1)
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER 8.4.6 Timer 1 Data Register (TDR1) The timer 1 data register (TDR1) is used to set the timer 1 value in the 8-bit mode of the 8/16-bit capture timer/counter or the interval timer value (interval timer function) or counter value (counter function) of the higher 8 bits in the 16-bit mode.
Page 197 ● 16-bit mode The values in TDR1 are compared with the counter values in the higher 8 bits of the 16-bit timer. When the interval timer function is used, the higher 8 bits of the interval time are set. When the counter function is used, the higher 8 bits of the count value to be detected are set.
Page 198: Capture Data Registers H And L (Tcph And Tcpl)
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER 8.4.7 Capture Data Registers H and L (TCPH and TCPL) The capture data register H (TCPH) stores the number of events of the higher 8 bits in the 16-bit capture mode of the 8/16-bit capture timer/counter. The capture data register L (TCPL) stores the number of events in the 8-bit capture mode of the 8/16-bit capture timer/counter or the number of events of the lower 8 bits in the 16-bit capture mode.
Page 199: 8/16-Bit Capture Timer/Counter Of Interrupts
8/16-bit Capture Timer/Counter of Interrupts The 8/16-bit capture timer/counter generates an interrupt if the values set in a data register match those set in the counter when the interval timer or counter is operating. The interrupt level is IRQ3 when generated by the 8/16-bit capture timer/counter. When the capture is in operation and a capture edge is detected, IRQ4 is generated.
Page 200 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Notes: • When the counter value matches the TDR0 value and at the same time the counter stops (TCR0: TSTR0 = 0), the TIF0 bit is not set. If the T0IEN bit is set to "1" (enable) when the TIF0 bit is "1", an interrupt request is generated immediately.
Page 201: Explanation Of Operations Of Interval Timer Functions
Explanation of Operations of Interval Timer Functions This section describes the interval timer function operation of the 8/16-bit capture timer/ counter. ■ Interval Timer Function Operation ● 8-bit mode To operate timer 0 as the interval timer function in the 8-bit mode, the function must be set as shown in Figure 8.6-1 .
Page 202 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Figure 8.6-2 Setting of Interval Timer Function (Timer 1) bit7 CPIF TCCR TCR1 TIF1 TCR0 TIF0 TCR2 TDR1 : Used bit : Unused bit When the counter is activated in the 8-bit mode, increment begins at the rising or falling edge of the selected clock, starting at 00 (comparator data latch), the interrupt request bit (TCR0: TIF0 or TCR1: TIF1) of the timer 0 control register is set to "1"...
Page 203 Figure 8.6-3 Interval Timer Function Operation in 8-bit Mode (Timer 0) Comparison Counter value value TDR0 value TDR0 value TIF0 bit Start Match (*2) Counter clear TSTR0 bit TO pin *1: If the data register is rewritten when the counter is in operation, the interval timer function becomes valid from the next cycle.
Page 204 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ● 16-bit mode To operate timer 0 as the interval timer function in the 16-bit mode, the function must be set as shown in Figure 8.6-4 . Figure 8.6-4 Setting of Interval Timer Function in 16-bit Mode bit7 CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TCCR...
Page 205: Operation Of Counter Functions
Operation of Counter Functions This section describes the operation of the 8/16-bit capture timer/counter function. ■ Counter Function Operation ● 8-bit mode To operate timer 0 as the counter function in the 8-bit mode, the function must be set as shown in Figure 8.7-1 .
Page 206 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ● Detection of the number of events In the external clock mode, counter clear can be prohibited by the compare match counter clear mask bit (TCMSK) of the capture control register (TCCR) when a match is detected. Setting the compare match counter clear mask bit to "1"...
Page 207 ● 16-bit mode To operate timer 0 as the counter function in the 16 bit mode, the function must be set as shown in Figure 8.7-3 . Figure 8.7-3 Setting of Counter Function in 16-bit Mode bit7 bit6 DDR3 CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 TCCR CPIF TFCR1 T1IEN...
Page 208 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER Figure 8.7-4 Counter Function Operation in 16-bit Mode External clock Counter clear TSTR0 bits Counter value Comparator data latch 1 (lower 8-bit comparison value) Comparator data latch 2 (higher 8-bit comparison value) Load TDR0 * (lower 8-bit setting value) TDR1 * (higher 8-bit setting value)
Page 209: Functions Of Operations Of Capture Functions
Functions of Operations of Capture Functions This section describes the capture function operation of the 8/16-bit capture timer/ counter. ■ Capture Function Operation ● 8-bit mode To operate the capture function in the 8-bit mode, the function must be set as shown in Figure 8.8-1 . Figure 8.8-1 Setting of Capture Function in 8-bit Mode bit7 DDR3...
Page 210 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ● Free-run mode Setting the clear mask bits (CCMSK and TCMSK) of TCCR to 11 as the free-run timer. ● Clear mode Setting the clear mask bits (CCMSK and TCMSK) of TCCR to a value other than 11 function to operate as a clear mode.
Page 211 Figure 8.8-2 Capture Mode Operation Counter clear FFFF TDR0 Compare latch Count value 0000 Capture latch Capture input (EC) TSTR0 TIF0 CPIF CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER TFCR0 = 1 (W) CFCLR = 1 (W) CCMSK=0 TCMSK=0 TFCR0 = 1 (W) CFCLR= 1 (W) CCMSK=1 CCMSK=1...
Page 212 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ● 16-bit mode To operate the capture function in the 16-bit mode, the function must be set as shown in Figure 8.8-3 . Figure 8.8-3 Setting of Capture Function in 16-bit Mode bit7 DDR3 TCCR CPIF CFCLR CPIEN CCMSK TCMSK EDGS1 EDGS0 RESV TIF1 TFCR1 T1IEN TCR1...
Page 213: 8/16-Bit Capture Timer/Counter Operation In Each Mode
8/16-bit Capture Timer/Counter Operation in Each Mode This section describes the operation of the 8/16-bit capture timer/counter when it switches to the sleep or stop mode or when a halfway stop request is issued during the operation of the interval timer or counter function. ■...
Page 214: Notes On Using 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER 8.10 Notes on Using 8/16-bit Capture Timer/Counter This section provides notes on using the 8/16-bit capture timer/counter. ■ Notes on Using the 8/16-bit Capture Timer/Counter ● Error The start of the 8/16-bit capture timer/counter by a program is asynchronous with the start of the counter incremented by the selected count clock, and therefore, the error (a time difference) continues until the counter value matches the set data.
Page 215 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER When the counter operation stops according to the timer start bits (TCR0: TSTR0 = 0 and TCR1: TSTR1 = 0) and the interrupt source occurs at the same time, the interrupt request flag bits (TCR0: TIF0 and TCR1: TIF1) are not set.
Page 216: Program Example For 8/16-Bit Capture Timer/Counter
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER 8.11 Program Example for 8/16-bit Capture Timer/Counter This section provides program examples of the 8/16-bit capture timer/counter. ■ Program Example of Interval Timer Function ● Processing specifications • In the 8-bit mode, only timer 0 is used to generate a 20 ms interval timer interrupt. •...
Page 217 TCR2,#00000010B TCR0,#10101011B SETI ;------------------------Interrupt program---------------------------------------------------------------------------- WARI CLRB TIF0 PUSHW XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ; -------------------------------------------------------------------------------------------------------------------- CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ; Outputs a square wave (TO) from the P34 pin. ; Allows timer 0 interrupt request output, clears the counter, and starts the timer.
Page 218: Program Example Of Counter Function
CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ■ Program Example of Counter Function ● Processing specifications • In the 16-bit mode, timer 0 and timer 1 are used to generate an interrupt whenever the external clock to be input to the EC pin is counted 5,000 times (1388 •...
Page 219 XCHW INCW CMPW READ16 RET16 ;------------------------Interrupt program---------------------------------------------------------------------------- WARI CLRB TIF0 PUSHW XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ; -------------------------------------------------------------------------------------------------------------------- CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER ; Old value + 1 ; Jumps to re-read when a mismatch is detected. ;...
Page 220 CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER...
Page 221: 12-Bit Ppg Timer
CHAPTER 9 12-BIT PPG TIMER This chapter describes the functions and operation of a 12-bit PPG timer. 9.1 Overview of 12-bit PPG Timer 9.2 Configuration of 12-bit PPG Timer Circuit 9.3 Pin of 12-bit PPG Timer 9.4 Registers of 12-bit PPG Timer 9.5 Operations of 12-bit PPG Timer Functions 9.6 Notes on Using 12-bit PPG Timer 9.7 Program Example for 12-bit PPG Timer...
Page 222: Overview Of 12-Bit Ppg Timer
CHAPTER 9 12-BIT PPG TIMER Overview of 12-bit PPG Timer The 12-bit PPG timer is a 12-bit binary counter, enabling the selection of one of four types of internal count clocks. The timer is capable of setting a cycle period and "H" width of output pulse waveforms and can also be used as a remote control transmission frequency generator or 12-bit PPG.
Page 223 Cycle period = Compare value for cycle period × Count clock cycle period "H" width = Compare value for "H" width × Count clock cycle period If the set "H" width is equal to or greater than the set cycle period, "H" level outputs occur. ■...
Page 224 CHAPTER 9 12-BIT PPG TIMER Table 9.1-2 Resolutions and Output Pulse Cycle Periods Supported when the Timer is Used as a 12-bit PPG (2/2) Range of Compare available value for compare Count clock cycle values for = 2 t period "H"...
Page 225: Configuration Of 12-Bit Ppg Timer Circuit
Configuration of 12-bit PPG Timer Circuit The 12-bit PPG timer comprises the following seven blocks: • Count clock selector • 12-bit counter • Comparator • 12-bit PPG control register 1 (RCR21) • 12-bit PPG control register 2 (RCR22) • 12-bit PPG control register 3 (RCR23) •...
Page 226 CHAPTER 9 12-BIT PPG TIMER ● Count clock selector This selector circuit selects one of four types of internal count clocks as the count-up clock for a 12-bit counter. ● 12-bit counter The 12-bit counter executes a count-up operation based on the count clock selected by the count clock selector.
Page 227: Pin Of 12-Bit Ppg Timer
Pin of 12-bit PPG Timer This section describes the pin associated with the 12-bit PPG timer and illustrates a block diagram of circuitry terminating at the pin. ■ Pin Associated with the 12-bit PPG Timer The pin associated with the 12-bit PPG timer is P37/BZ/PPG pin. ●...
Page 228 CHAPTER 9 12-BIT PPG TIMER ■ Block Diagram of Circuitry Terminating at the Pin Associated with the 12-bit PPG Timer Figure 9.3-1 Block Diagram of Circuitry Terminating at the P37/BZ/PPG Pin PDR read PDR read (when read-modify-write is performed) Output latch PDR write DDR write PUL read...
Page 229: Registers Of 12-Bit Ppg Timer
Registers of 12-bit PPG Timer This section describes the registers associated with the 12-bit PPG timer. ■ Registers Associated with 12-bit PPG Timer Figure 9.4-1 Registers Associated with 12-bit PPG Timer RCR21 (12-bit PPG control register 1) Address bit7 0014 RCK1 RCK0 RCR22 (12-bit PPG control register 2) Address...
Page 230: 12-Bit Ppg Control Register 1 (Rcr21)
CHAPTER 9 12-BIT PPG TIMER 9.4.1 12-bit PPG Control Register 1 (RCR21) The 12-bit PPG control register 1 comprises bits for count clock selection of the 12-bit PPG timer and bits for setting the "H" width. ■ 12-bit PPG Control Register 1 (RCR21) Figure 9.4-2 12-bit PPG Control Register 1 (RCR21) Address bit7...
Page 231: 12-Bit Ppg Control Register 2 (Rcr22)
9.4.2 12-bit PPG Control Register 2 (RCR22) The 12-bit PPG control register 2 comprises bits for setting the "H" width of 12-bit PPG pulse waveforms. ■ 12-bit PPG Control Register 2 (RCR22) Figure 9.4-3 12-bit PPG Control Register 2 (RCR22) Address bit7 bit6...
Page 232: 12-Bit Ppg Control Register 3 (Rcr23)
CHAPTER 9 12-BIT PPG TIMER 9.4.3 12-bit PPG Control Register 3 (RCR23) The 12-bit PPG control register 3 comprises a bit for enabling 12-bit PPG waveform outputs and bits for setting a cycle period of outputs. ■ 12-bit PPG Control Register 3 (RCR23) Figure 9.4-4 12-bit PPG Control Register 3 (RCR23) Address bit7...
Page 233 Table 9.4-3 Explanation of Functions of Each Bit in 12-bit PPG Control Register 3 (RCR23) Bit name RCEN: bit7 Output enable bit bit6 Unused bit bit5 SCL5 to SCL0: Cycle period bit0 setting bits Note: Because buzzer outputs to the P37/BZ/PPG pin precede 12-bit PPG outputs to this pin, if the pin is used as the PPG pin, turn the buzzer outputs off and set the RCEN bit such that PPG outputs are enabled.
Page 234: 12-Bit Ppg Control Register 4 (Rcr24)
CHAPTER 9 12-BIT PPG TIMER 9.4.4 12-bit PPG Control Register 4 (RCR24) The 12-bit PPG control register 4 comprises bits for setting a cycle period of 12-bit PPG waveform outputs. ■ 12-bit PPG Control Register 4 (RCR24) Figure 9.4-5 12-bit PPG Control Register 4 (RCR24) Address bit7 bit6...
Page 235: Operations Of 12-Bit Ppg Timer Functions
Operations of 12-bit PPG Timer Functions The 12-bit PPG timer can be used as a 12-bit PPG because the output pulse cycle period and "H" pulse width can be set separately. ■ Example of Operations of 12-bit PPG Timer Functions To operate the 12-bit PPG timer, the bits of the registers must be set as shown in Figure 9.5-1 .
Page 236 CHAPTER 9 12-BIT PPG TIMER Figure 9.5-2 illustrates the operation of the 12-bit PPG timer. Count by counter Cycle period setting (RCR23, 24:SCL0 to SCL11) "H" width setting (RCR21, 22:HSC0 to HSC11) "000 PPG output pulse waveform If internal count clock cycle period is 2, 4, 16, or 256 t period multiplied by the count clock cycle period.
Page 237: Notes On Using 12-Bit Ppg Timer
Notes on Using 12-bit PPG Timer This section provides notes on using the 12-bit PPG timer. ■ Notes on Using 12-bit PPG Timer ● Output pin changeover The P37/BZ/PPG pin shares functions of a general-purpose port and a 12-bit PPG output. Because its buzzer output (BZ) function precedes the 12-bit PPG output function, if buzzer outputs are enabled, it functions as the buzzer output (BZ) pin even if PPG outputs are enabled by the RCR23 (RCEN bit).
Page 238 CHAPTER 9 12-BIT PPG TIMER Figure 9.6-1 Setting Change during 12-bit PPG Timer Operation Count by counter "FFF" Cycle period setting (RCR23,24:SCL0 to SCL11) "H" width setting (RCR21,22:HSC0 to HSC11) "00" PPG output pulse waveform Because the count interval of the operating counter is less than the changed setting, the setting is effective only within the cycle.
Page 239: Program Example For 12-Bit Ppg Timer
Program Example for 12-bit PPG Timer An example of 12-bit PPG timer programming is given below. ■ Program Example for 12-bit PPG Timer ● Processing specification A remote control transmission frequency with a period of about 38 µs and a duty cycle of approx. 33% •...
Page 240 CHAPTER 9 12-BIT PPG TIMER...
Page 241: Chapter 10 External Interrupt Circuit 1 (Edge)
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) This chapter describes the function and operation of external interrupt circuit 1 (edge). 10.1 Overview of External Interrupt Circuit 1 10.2 Configuration of External Interrupt Circuit 1 10.3 Pins of External Interrupt Circuit 1 10.4 Registers of External Interrupt Circuit 1 10.5 Interrupt of External Interrupt Circuit 1 10.6 Operations of External Interrupt Circuit 1...
Page 242: Overview Of External Interrupt Circuit 1
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.1 Overview of External Interrupt Circuit 1 External interrupt circuit 1 detects a predetermined edge or edges of a signal input to any of three external interrupt pins and then generates and issues an interrupt request to the CPU.
Page 243: Configuration Of External Interrupt Circuit 1
10.2 Configuration of External Interrupt Circuit 1 External interrupt circuit 1 comprises the following two blocks: • Edge detecting circuits (0 to 2) • External interrupt control 1 registers 1, 2 (EIC1, EIC2) ■ Block Diagram of External Interrupt Circuit 1 Figure 10.2-1 Block Diagram of External Interrupt Circuit 1 (EIC1, EIC2) P34/TO/INT10 Edge detecting circuit 1...
Page 244 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ● Edge detecting circuits When the edge polarity of a signal input to one of the pins (INT10 to INT12) for external interrupt circuit 1 matches the selected edge polarity for the pin, stored in either the EIC1 or EIC2 registers in the appropriate bit position (SL00 to SL21), one of the external interrupt request flag bits (EIR0 to EIR2) corresponding to the pin is set to "1".
Page 245: Pins Of External Interrupt Circuit 1
10.3 Pins of External Interrupt Circuit 1 This section describes the pins associated with external interrupt circuit 1 and illustrates a block diagram of circuitry terminating at the pins with reference to the registers and external interrupt triggering. ■ Pins Associated with External Interrupt Circuit 1 The pins associated with external interrupt circuit 1 are the P34/TO/INT10 to P36/INT12 pins.
Page 246 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ■ Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 Figure 10.3-1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 PDR read PDR read (when read-modify-write is performed)
Page 247: Registers Of External Interrupt Circuit 1
10.4 Registers of External Interrupt Circuit 1 This section describes the registers associated with external interrupt circuit 1. ■ Registers Associated with External Interrupt Circuit 1 Figure 10.4-1 Registers Associated with External Interrupt Circuit 1 EIC1 (External interrupt 1 control register 1) Address bit7 0024...
Page 248: External Interrupt Control Register 1 (Eic1)
CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) 10.4.1 External Interrupt Control Register 1 (EIC1) External interrupt control register 1 (EIC1) comprises bits for edge polarity selection and interrupt control for the INT10 and INT11 external interrupt pins. ■ External Interrupt Control Register 1 (EIC1) Figure 10.4-2 External Interrupt Control Register 1 (EIC1) Address bit7...
Page 249 Table 10.4-1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 (EIC1) (1/2) Bit name EIR1: bit7 External interrupt request flag bit1 SL11, SL10: bit6, Edge polarity bit5 selection bits 1 EIE1: bit4 Interrupt request enable bit 1 EIR0: bit3 External interrupt...
Page 250 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Table 10.4-1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 (EIC1) (2/2) Bit name EIE0: bit0 Interrupt request enable bit 0 This bit enables or disables interrupt request outputs to the CPU. When this bit and external interrupt request flag bit 0 (EIR0) are "1", the interrupt request is output.
Page 251: External Interrupt Control Register 2 (Eic2)
10.4.2 External Interrupt Control Register 2 (EIC2) As with external interrupt control register 1 (EIC1), external interrupt control register 2 (EIC2) comprises bits for edge polarity selection and interrupt control for the INT12 external interrupt pin. ■ External Interrupt Control Register 2 (EIC2) Figure 10.4-3 External Interrupt Control Register 2 (EIC2) Address bit7...
Page 252 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Table 10.4-2 Explanation of Functions of Each Bit in External Interrupt Control Register 2 (EIC2) Bit name bit7 Unused bits bit4 EIR2: bit3 External interrupt request flag bit 2 SL21, SL20: bit2 Edge polarity selection bit1 bits 2 EIE2:...
Page 253: Interrupt Of External Interrupt Circuit 1
10.5 Interrupt of External Interrupt Circuit 1 The detection of a signal with the specified edge or edges, input to any of the external interrupt pins, triggers external interrupt circuit 1 to generate an interrupt request. ■ Interrupt during the Operation of External Interrupt Circuit 1 When external interrupt circuit 1 detects the specified edge or edges of external interrupt input at a pin, an external interrupt request flag bit (EIC1, EIC2:EIR0 to EIR2) corresponding to the pin is set to "1".
Page 254 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) ■ Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Table 10.5-1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Interrupt designation Register IRQ0 IRQ1 ILR1 (007B IRQ2...
Page 255: Operations Of External Interrupt Circuit 1
10.6 Operations of External Interrupt Circuit 1 The external interrupt circuit 1 can detect a specified edge or edges of a signal input to any of the external interrupt pins. ■ Operation of External Interrupt Circuit 1 To operate external interrupt circuit 1, the bits of the registers must be set as shown in Figure 10.6-1 . Figure 10.6-1 Setting External Interrupt Circuit 1 bit7 EIC1...
Page 256 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) Figure 10.6-2 shows the operation when an external interrupt is input to the INT10 pin. Figure 10.6-2 Operation of External Interrupt 1 (INT10) Pulse waveform input to INT10 pin Cleared when EIE0 bit is set EIR0 bit EIE0 bit...
Page 257: Program Example For External Interrupt Circuit 1
10.7 Program Example for External Interrupt Circuit 1 An example of programming external interrupt circuit 1 is given below. ■ External Interrupt Circuit 1 Programming Example ● Processing specification External interrupt circuit 1 detects the rising edge of a pulse input to the INT10 pin and generates an interrupt.
Page 258 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE) PUSHW User processing POPW XCHW POPW RETI ENDS ;--------------------------------------------------------------------------------------------------------------------...
Page 259: Chapter 11 External Interrupt Circuit 2 (Level)
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) This chapter describes the function and operation of an external interrupt circuit 2 (level). 11.1 Overview of External Interrupt Circuit 2 11.2 Configuration of External Interrupt Circuit 2 11.3 Pins of External Interrupt Circuit 2 11.4 Registers of External Interrupt Circuit 2 11.5 Interrupt of External Interrupt Circuit 2 11.6 Operations of External Interrupt Circuit 2...
Page 260: Overview Of External Interrupt Circuit 2
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.1 Overview of External Interrupt Circuit 2 External interrupt circuit 2 detects the predetermined level of a signal input to any of the eight external interrupt pins and generates and issues an interrupt request to the CPU. ■...
Page 261: Configuration Of External Interrupt Circuit 2
11.2 Configuration of External Interrupt Circuit 2 The external interrupt circuit 2 comprises the following three blocks: • Interrupt request generating circuit • External interrupt 2 control register (EIE2) • External interrupt 2 flag register (EIF2) ■ Block Diagram of External Interrupt Circuit 2 Figure 11.2-1 Block Diagram of External Interrupt Circuit 2 External interrupt 2 control register (EIE2) IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20...
Page 262: Pins Of External Interrupt Circuit 2
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.3 Pins of External Interrupt Circuit 2 This section describes the pins associated with external interrupt circuit 2 and illustrates a block diagram of circuitry terminating at the pins with reference to the registers and interrupt triggering.
Page 263 ■ Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 Figure 11.3-1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt PDR read PDR read (when read-modify-write is performed) PDR write DDR write PUL read PUL write SPL: Pin status setting bit of standby control register (STBC)
Page 264 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) ■ Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins The interrupt enable bits are associated with the external interrupt pins as listed in Table 11.3-2 . Table 11.3-2 Correspondence between the External Interrupt Enable Bits and the External Interrupt Pins Register...
Page 265: Registers Of External Interrupt Circuit 2
11.4 Registers of External Interrupt Circuit 2 The external interrupt 2 control register (EIE2) is used to enable or disable the external interrupt pins. ■ Registers Associated with External Interrupt Circuit 2 Figure 11.4-1 Registers Associated with External Interrupt Circuit 2 EIE2 (External interrupt 2 control register) Address bit7...
Page 266: External Interrupt 2 Control Register (Eie2)
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.4.1 External Interrupt 2 Control Register (EIE2) The external interrupt circuit 2 control register (EIE2) enables or disables the interrupt inputs to the external interrupt pins INT20 to INT27. ■ External Interrupt Circuit 2 Control Register (EIE2) Figure 11.4-2 External Interrupt Circuit 2 Control Register (EIE2) bit7 bit6...
Page 267 Table 11.4-2 Functions of the Bits of the External Interrupt 2 Control Register (EIE2) Bit name bit7 IE27 to IE20: External interrupt bit0 input enable bits CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) Function • These bits enable or disable the interrupt inputs to external interrupt pins INT20 to INT27.
Page 268: External Interrupt 2 Flag Register (Eif2)
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.4.2 External Interrupt 2 Flag Register (EIF2) The external interrupt 2 flag register (EIF2) is used to hold the interrupt state by flagging an interrupt request flag when a level interrupt is detected and then clearing the flag. ■...
Page 269: Interrupt Of External Interrupt Circuit 2
11.5 Interrupt of External Interrupt Circuit 2 An "L" level input signal input to one of the external interrupt pins triggers external interrupt circuit 2 to generate an interrupt. ■ Interrupt during the Operation of External Interrupt Circuit 2 When an "L" level signal is input to one of the external interrupt pins for which interrupt inputs are enabled, the external interrupt request flag bit (EIF2:IF20) is set to "1"...
Page 270: Operations Of External Interrupt Circuit 2
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.6 Operations of External Interrupt Circuit 2 External interrupt circuit 2 detects "L" level at any of the external interrupt pins, then generates and issues an interrupt request to the CPU. ■ Operation of External Interrupt Circuit 2 To operate the external interrupt circuit 2, the bits of the registers must be set as shown in Figure 11.6-1 .
Page 271 Figure 11.6-2 Operation of External Interrupt 2 (INT20) Pulse waveform input to INT20/AN4 pin (Detection of the "L" level) EIE2:IE20 EIF2:IF20 (IRQA state also changes accordingly.) Operation of interrupt processing routine for IRQA Can be read at any time. PDR0:bit0 Note: Even when the pin is used as an external interrupt input pin, the pin state can be read directly from the port 0 data register (PDR0).
Page 272: Program Example For External Interrupt Circuit 2
CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL) 11.7 Program Example for External Interrupt Circuit 2 An example of programming external interrupt circuit 2 is given below. ■ Program Example for External Interrupt Circuit 2 ● Processing specification The external interrupt circuit 2 detects an "L" level signal input to the P00/INT20/AN4 pin and generates an interrupt.
Page 273 PUSHW XCHW PUSHW User processing POPW XCHW POPW RETI ENDS ;-------------------------------------------------------------------------------------------------------------------- CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Page 274 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
Page 275: Chapter 12 A/D Converter
CHAPTER 12 A/D CONVERTER This chapter describes the functions and operations of the A/D converter. 12.1 Overview of A/D Converter 12.2 Configuration of A/D Converter 12.3 Pins of A/D Converter 12.4 Registers of A/D Converter 12.5 Interrupt of A/D Converter 12.6 Operations of A/D Converter Functions 12.7 Notes on Using A/D Converter 12.8 Program Example for A/D Converter...
Page 276: Overview Of A/D Converter
CHAPTER 12 A/D CONVERTER 12.1 Overview of A/D Converter An A/D converter, which is of a 10-bit successive approximation type, selects an input signal from eight channel analog inputs. The A/D converter can be activated with software, an internal clock, or the output of an 8/16-bit capture timer/counter (16-bit mode).
Page 277: Configuration Of A/D Converter
12.2 Configuration of A/D Converter The A/D converter consists of the following nine blocks. • Clock selector (input clock selector for activation of A/D conversion) • Analog channel selector • Sample hold circuit • D/A converter • Comparator • Control circuit •...
Page 278 CHAPTER 12 A/D CONVERTER ● Clock selector The clock selector selects the clock to be used to activate A/D conversion while continuous activation is enabled (ADC2: EXT = 1). ● Analog channel selector This circuit selects one out of the eight analog inputs. ●...
Page 279: Pins Of A/D Converter
12.3 Pins of A/D Converter This section describes the pins related to the A/D converter and shows a block diagram of the pins related to the A/D converter. ■ Pins Related to the A/D Converter The pins related to the A/D converter are P03/INT23/AN7 to P00/INT20/AN4, and P43/AN3 to P40/AN0 pins.
Page 280 CHAPTER 12 A/D CONVERTER ■ Block Diagram of the Pins Related to the A/D Converter Figure 12.3-1 Block Diagram of P03/INT23/AN7 to P00/INT20/AN4 Pins PDR read PDR read (At read-modify-write) PDR write DDR write PUL read PUL write SPL: Pin status setting bit of the standby control register (STBC) Figure 12.3-2 Block Diagram of P43/AN3 to P40/AN0 Pins PDR read PDR read...
Page 281: Registers Of A/D Converter
12.4 Registers of A/D Converter Figure 12.4-1 shows the registers related to the A/D converter. ■ Registers Related to the A/D Converter Figure 12.4-1 Registers Related to the A/D Converter ADC1 (A/D control register 1) Address bit7 0030 ADC2 (A/D control register 2) Address bit7 0031...
Page 282: A/D Control Register 1 (Adc1)
CHAPTER 12 A/D CONVERTER 12.4.1 A/D Control Register 1 (ADC1) A/D control register 1 (ADC1) is used to set the enabling and disabling functions of the A/D converter, select an analog input, and check the status. ■ A/D Control Register 1 (ADC1) Address bit7 bit6...
Page 283 Table 12.4-1 Explanation of Functions of Each Bit in the Bits in A/D Control Register 1 (ADC1) Bit name bit7 Unused bit bit6 ANS2, ANS1, ANS0: Analog input channel bit4 selection bits ADI: bit3 Interrupt request flag ADMV: bit2 Convertion flag bit RESV0: bit1 Reserved bit...
Page 284: A/D Control Register 2 (Adc2)
CHAPTER 12 A/D CONVERTER 12.4.2 A/D Control Register 2 (ADC2) A/D control register 2 (ADC2) is used to select an input clock, enable and disable an interrupt and continuous activation. ■ A/D Control Register 2 (ADC2) Address bit7 bit6 bit5 0031 RESV4 RESV3 ADCK R/W : Readable/ Writable...
Page 285 Table 12.4-2 Explanation of Functions of Each Bit in A/D Control Register 2 (ADC2) Bit name bit7 Unused bit bit6, RESV4,RESV3: bit5 Reserved bits bit4 ADCK: Selecting an input clock bit ADIE: bit3 Enabling an interrupt request bit RESV2: bit2 Reserved bit EXT: bit1...
Page 286: A/D Data Register (Addh And Addl)
CHAPTER 12 A/D CONVERTER 12.4.3 A/D Data Register (ADDH and ADDL) A/D data register (ADDH and ADDL) stores the results of A/D conversion at 10-bit A/D conversion. The high-order 2 bits of 10-bit data correspond to the ADDH register. The low-order 8 bits correspond to the ADDL register.
Page 287: A/D Enable Register (Aden)
12.4.4 A/D Enable Register (ADEN) The ADEN register is used to select the analog input port that corresponds to different pins. Writing "1" to an appropriate ADEN register bit enables analog input. ■ A/D Enable Register (ADEN) Figure 12.4-5 shows the bit configuration of the A/D enable register. Address bit7 bit6...
Page 288: Interrupt Of A/D Converter
CHAPTER 12 A/D CONVERTER 12.5 Interrupt of A/D Converter A factor for an interrupt of the A/D converter is the following. • Completion of conversion when A/D conversion functions are enabled ■ Interrupt when A/D Conversion Functions are Enabled When A/D conversion is completed, the interrupt request flag bit (ADC1: ADI) is set to "1". At this time, if the bit for enabling an interrupt request is enabled (ADC2: ADIE = 1), an interrupt request to the CPU (IRQ8) occurs.
Page 289: Operations Of A/D Converter Functions
12.6 Operations of A/D Converter Functions The A/D converter can be activated with software or activated continuously. ■ Activating the A/D Converter Functions ● Software activation To activate A/D conversion functions with software, set registers as shown in Figure 12.6-1 . Figure 12.6-1 Setting A/D Conversion Functions (at Software Activation) ADC1 ADC2...
Page 290: Operations Of A/D Conversion Functions
CHAPTER 12 A/D CONVERTER Figure 12.6-2 Setting A/D Conversion Functions (at Continuous Activation) ADC1 ADC2 ADDH ADDL ADEN : Used bit : Unused bit : Set "1" : Set "0" : Set "1" to an appropriate bit When continuous activation is enabled, A/D conversion is activated on a rising edge of the selected input clock and the operations of A/D conversion functions are started.
Page 291: Notes On Using A/D Converter
12.7 Notes on Using A/D Converter This section describes notes on using the A/D converter. ■ Notes on Using the A/D Converter ● Input impedance of the analog input The A/D converter contains the sample hold circuit as shown in Figure 12.7-1 , captures the voltage of the analog input, and holds it in the capacitor for sample hold in about 16 instruction cycles, after activation of A/D conversion.
Page 292 CHAPTER 12 A/D CONVERTER ● Notes on interrupt requests If A/D conversion is reactivated (ADC1: AD = 1) and terminated at the same time, the interrupt request flag bit (ADC1: ADI) is not set. ● Conversion time Changing the oscillation frequency or clock speed (gear functions) affects the conversion speed of A/D conversion functions.
Page 293: Program Example For A/D Converter
12.8 Program Example for A/D Converter This section shows a program example of the 10-bit A/D converter. ■ Program Example of the A/D Conversion Functions ● Processing specifications The analog voltage to be applied to the AN0 pin is converted to digital voltage through software activation. In this example, completion of conversion is detected in a loop in the program without using interrupts.
Page 294 CHAPTER 12 A/D CONVERTER ENDS ;-------------------------------------------------------------------------------------------------------------------- A,ADDL ; Reads A/D conversion data (low-order 8 bits). A,ADDH ; Reads A/D conversion data (high-order 2 bits).
Page 295: Chapter 13 Uart
CHAPTER 13 UART This chapter describes the functions and operations of UART. 13.1 Overview of UART 13.2 Configuration of UART 13.3 Pins of UART 13.4 Registers of UART 13.5 Interrupt of UART 13.6 Operations of UART Functions 13.7 Program Example for UART...
Page 296: Overview Of Uart
CHAPTER 13 UART 13.1 Overview of UART UART is a general-purpose communication interface for serial data. UART allows variable-length serial data to be transferred synchronously or asynchronously with a clock. The transfer format is NRZ. The dedicated baud rate generator, external clock, or internal timer (8-bit PWM timer) settings determine the data transfer format.
Page 297 ■ Serial Switch UART and 8-bit serial I/O use the same pins, thus they cannot be simultaneously used. The serial switch circuit needs be used to select either of them. When UART is selected using the serial switch, P30/UCK/SCK is used as the UART serial clock I/O pin (UCK), P31/UO/SO is used as the UART data output pin (UO), and P32/UI/SI is used as the UART data input pin (UI).
Page 298 CHAPTER 13 UART Figure 13.1-2 Example of Calculating the Baud Rate Clock gear selected , 8/F Value of baud rate , 64/ Notes: The baud rate is specified using the clock gear register (CS1 and CS0), clock divider registers (PR2, PR1, and PR0), or baud rate selection registers (RC2, RC1, and RC0).
Page 299 Table 13.1-4 provides an example of the baud rates selectable when the 8-bit PWM timer is used. Table 13.1-4 Transfer Cycles and Transfer Rates Selectable for the 8-bit PWM Timer Asynchronous transfer mode PWM timer count clock cycle Divider for clock CR=0 INST CR=1...
Page 300: Configuration Of Uart
CHAPTER 13 UART 13.2 Configuration of UART UART consists of the following ten registers and components: • Serial mode control register (SMC) • Serial rate control register (SRC) • Serial status and data register (SSD) • Serial input data register (SIDR) •...
Page 301 ● Serial mode control register (SMC) The SMC register controls UART operating mode. This register specifies the parity setting, stop bit length, operating mode (data length), and synchronous/asynchronous mode, and enables/disables UART serial clock output and serial data output. ● Serial rate control register (SRC) The SRC register controls the UART data transfer speed (baud rate).
Page 302 CHAPTER 13 UART ● UART interrupt sources [Reception] When data with the specified length is correctly received or when the overrun error or framing error occurs while data is being received, the reception interrupt request (IRQ6) is generated if the reception interrupt request is enabled (SSD: RIE = 1).
Page 303: Pins Of Uart
13.3 Pins of UART Pins relating to UART are the clock I/O pin (P30/UCK/SCK), serial data output pin (P31/UO/SO), and serial data input pin (P32/UI/SI). ■ UART Relating Pins ● P30/UCK/SCK This pin functions as the general-purpose I/O port (P30), UART clock I/O pin (UCK), or 8-bit serial clock I/O pin (SCK).
Page 304 CHAPTER 13 UART ■ Block Diagram of the UART-relating Pins Figure 13.3-1 Block Diagram of UART-relating Pins PDR read PDR read (At read-modify-write) PDR write DDR write PUL read PUL write When use of the pull-up resistor is selected in the pull-up setting register, the pin status does not become Hi-Z but "H"...
Page 305: Registers Of Uart
13.4 Registers of UART Figure 13.4-1 shows the UART-relating registers. ■ UART-relating Registers SMC (serial mode control register) Address bit7 0028 SRC (serial rate control register) Address bit7 0029 SSD (serial status and data register) Address bit7 002A RDRF ORFE SIDR (serial input data register) Address bit7...
Page 306: Serial Mode Control Register (Smc)
CHAPTER 13 UART 13.4.1 Serial Mode Control Register (SMC) The serial mode control register (SMC) specifies the parity setting, stop bit length, operating mode (data length), and synchronous/asynchronous mode, and enables/ disables UART serial clock output and serial data output. ■...
Page 307 Table 13.4-1 Explanation of Functions of Each Bit in the Serial Mode Control Register (SMC) Bit name PEN: bit7 Parity enable bit SBL: bit6 Stop bit length selection bit bit5, MC1, MC0: bit4 Operating mode selection bits SMDE: bit3 Synchronization mode selection bit2 Unused bit SCKE:...
Page 308: Serial Rate Control Register (Src)
CHAPTER 13 UART 13.4.2 Serial Rate Control Register (SRC) The serial rate control register (SRC) controls the data transfer rate (baud rate) in asynchronous transfer mode. The SRC selects the input clock and sets the transfer rate for the dedicated baud rate generator. ■...
Page 309 Table 13.4-2 Explanation of Functions of Each Bit in the Serial Rate Control Register (SRC) Bit name bit7, Unused bits bit6 bit5 Clock rate input selection bit CS1,CS0: bit4, Clock input selection bit3 bits bit2 RC2,RC1,RC0: Baud rate selection bits bit0 •...
Page 310: Serial Status And Data Register (Ssd)
CHAPTER 13 UART 13.4.3 Serial Status and Data Register (SSD) The serial status and data register (SSD) controls data transmission/reception of UART and status in an error, enables/disables interrupts, and specifies and checks settings for parity or bit-8 transmitting data. ■...
Page 311 Table 13.4-3 Explanation of Functions of Each Bit in the Serial Status and Data Register (SSD) Bit name RDRF: bit7 Received data flag bit ORFE: bit6 Overrun/Framing error flag bit TDRE: bit5 Transmitted data flag TIE: bit4 Transmission interrupt request enable bit RIE: bit3 Reception interrupt...
Page 312: Receiving Status
CHAPTER 13 UART ■ Receiving Status Figure 13.4-5 shows the states (receiving status) of serial input data obtained from the received data flag bit (RDRF) and error flag bit (ORFE). RDRF ORFE : Initial value Figure 13.4-5 Receiving Status Received data flag bit/Overrun/Framing error flag bit No data Framing error Normal data...
Page 313: Serial Input Data Register (Sidr)
13.4.4 Serial Input Data Register (SIDR) The serial input data register (SIDR) is for inputting (receiving) serial data. ■ Serial Input Data Register (SIDR) Figure 13.4-6 shows the configuration of the serial input data register bits. Figure 13.4-6 Serial Input Data Register (SIDR) Address bit7 bit6...
Page 314: Serial Output Data Register (Sodr)
CHAPTER 13 UART 13.4.5 Serial Output Data Register (SODR) The serial output data register (SODR) sends out (transmits) serial data. ■ Serial Output Data Register (SODR) Figure 13.4-7 shows the configuration of the serial output data register bits. Figure 13.4-7 Serial Output Data Register (SODR) Address bit7 bit6...
Page 315: Clock Divider Selection Register (Upc)
13.4.6 Clock Divider Selection Register (UPC) The clock divider selection register is used to generate the UART reference clock by dividing the oscillation frequency. It also enables/disables operation of the prescaler for creating the reference clock. ■ Clock Divider Selection Register (UPC) Figure 13.4-8 Clock Divider Selection Register (UPC) Address bit7...
Page 316 CHAPTER 13 UART Table 13.4-4 Explanation of Functions of Each Bit in the Clock Divider Selection Register (UPC) Bit name bit7 Unused bits bit4 PREN: bit3 UART prescaler operation enable bit bit2 PR2, PR1, PR0: Clock divider selection bit0 bits Note: The inside of UART is initialized when it is in synchronization transfer mode, asynchronous transfer mode, external clock mode, or internal clock mode with the clock from the prescaler.
Page 317: Serial Switch Register (Ssel)
13.4.7 Serial Switch Register (SSEL) The serial switch register (SSEL) switches the P30/UCK/SCK, P31/UO/SO, and P32/UI/SI pins between UART and 8-bit serial I/O. ■ Serial Switch Register (SSEL) bit7 bit6 bit5 Address 003B : Readable/Writable : Unused : Initial value Table 13.4-5 Description of the Serial Switch Register (SSEL) Bits Bit name bit7...
Page 318 CHAPTER 13 UART Figure 13.4-10 Block Diagram of Serial Switch Register 8-bit serial I/O UART Internal data bus SSEL register SSEL bit Selector Selector Pin (P30/UCK/SCK) Port 3 Pin (P32/UI/SI) Pin (P31/UO/SO)
Page 319: Interrupt Of Uart
13.5 Interrupt of UART UART supports the interrupt-related error flag bit (ORFE), received data flag bit (RDRF), and transmitted data flag bit (TDRE), and the following interrupt sources: • When received data is sent from the reception shift register to the serial input data register (SIDR).
Page 320: Operations Of Uart Functions
CHAPTER 13 UART 13.6 Operations of UART Functions UART supports four types of operating mode. Mode 0, mode 1, and mode 3 are general serial transfer mode in which any data length can be selected in the range of 6 bits with parity used, to 9 bits without parity used.
Page 321 ■ Theory of Operation for Operating Mode 0, 1, 2, and 3 In operating mode 0, 1, 2, or 3, UART operates as a general serial communication function. Figure 13.6-2 shows the settings required in UART operating mode 0, 1, 2, or 3. bit7 RDRF SIDR...
Page 322: Transmission Operations (Operating Mode 0, 1, 2, And 3)
CHAPTER 13 UART 13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3) When writing data to be transmitted into the SODR register after reading the SSD register sends the data written into the SODR register to the transmission shift register, parallel-serial conversion then starts.
Page 323: Reception Operations (Operating Mode 0, 1, Or 3)
13.6.2 Reception Operations (Operating Mode 0, 1, or 3) When data is received at the serial data input pin, the internal reception shift register converts it from serial to parallel. If the data is correctly transmitted up to the stop bit(s), data in the internal shift register is transferred to the SIDR register, then "1"...
Page 324 CHAPTER 13 UART Figure 13.6-5 Operations in Operating Mode 0, 1, or 3 when the Overrun Error Occurs Data START RDRF=1 (reception buffer full) ORFE Reception interrupt Figure 13.6-6 Operations in Operating Mode 0, 1, or 3 when the Framing Error Occurs Data START RDRF=0...
Page 325: Reception Operations (Operating Mode 2 Only)
13.6.3 Reception Operations (Operating Mode 2 Only) When data is received at the serial data input pin, the internal reception shift register converts it from serial to parallel. If the data is correctly transmitted up to the stop bit(s), data in the internal shift register is transferred to the SIDR register, then "1" is set to the RDRF bit.
Page 326 CHAPTER 13 UART Figure 13.6-9 Operations in Operating Mode 2 when the Framing Error Occurs Data START RDRF=0 ORFE Reception interrupt Note: After initialization is cancelled due to a reset, time for 11 shift-clock cycles is required to initialize the internal controller.
Page 327: Program Example For Uart
13.7 Program Example for UART This section provides program example for UART. ■ Program Example for UART ● Program specifications • Serial data transfer is implemented using the UART communication functions. • The P30/UCK/SCK, P31/UO/SO, and P32/UI/SI pins are used for communication. •...
Page 328 CHAPTER 13 UART SETI ;--------------------Interrupt processing routine----------------------------------------------------------- WARI PUSHW A XCHW A,T PUSHW A User-defined process POPW XCHW A,T POPW RETI ENDS ; -------------------------------------------------------------------------------------------------------------------- mode 1. Set asynchronous mode, enable clock output and serial data output. SRC,#00011101B ; Select the dedicated baud rate generator, and set the baud rate 375 bps.
Page 329 CHAPTER 14 8-BIT SERIAL I/O This chapter describes the functions and operation of the 8-bit serial I/O. 14.1 Overview of 8-Bit Serial I/O 14.2 Configuration of 8-Bit Serial I/O 14.3 Pins of 8-Bit Serial I/O 14.4 Registers of 8-Bit Serial I/O 14.5 Interrupt of 8-Bit Serial I/O 14.6 Operations of Serial Output Functions 14.7 Operations of Serial Input Functions...
Page 330: Chapter 14 8-Bit Serial I/O
CHAPTER 14 8-BIT SERIAL I/O 14.1 Overview of 8-Bit Serial I/O The 8-bit serial I/O has a function that serially transfers 8-bit data in synchronization with a shift clock. It can select one shift clock from three internal shift clocks and one external shift clock.
Page 331: Configuration Of 8-Bit Serial I/O
14.2 Configuration of 8-Bit Serial I/O Each 8-bit serial I/O channel consists of the following four blocks: • Shift clock control circuit • Shift clock counter • Serial data register (SDR) • Serial mode register (SMR) ■ Block Diagram of 8-bit Serial I/O Figure 14.2-1 Block Diagram of 8-bit Serial I/O D0 to D7 MSB first...
Page 332 CHAPTER 14 8-BIT SERIAL I/O ● Shift clock control circuit As a shift clock of the shift clock control circuit, one of three internal clocks and one external clock is selected. Selecting an internal clock enables the shift clock to be output to the SCK pin. Selecting an external clock enables the clock to be input from the SCK pin to act as the shift clock.
Page 333: Pins Of 8-Bit Serial I/O
14.3 Pins of 8-Bit Serial I/O 8-bit serial I/O pins include P32/UI/SI, P31/UO/SO, and P30/UCK/SCK pins. ■ Pins of 8-bit Serial I/O ● P32/UI/SI pin The P32/UI/SI pin functions as the general-purpose I/O port (P32). It also functions as the serial data input pin (SI) of the 8-bit serial I/O or as the serial data input pin (UI) of the UART.
Page 334 CHAPTER 14 8-BIT SERIAL I/O ■ Block Diagram for 8-bit Serial I/O Pins Figure 14.3-1 Block Diagram for 8-bit Serial I/O Pins PDR read PDR read (At read-modify-write) Output latch PDR write DDR write PUL read PUL write Note: When "pull-up resistor available" is selected in the pull-up setting register, the pin state in stop mode (SPL = 1) becomes high (pull-up state), not Hi-Z.
Page 335: Registers Of 8-Bit Serial I/O
14.4 Registers of 8-Bit Serial I/O Figure 14.4-1 shows 8-bit serial I/O registers. ■ Registers of 8-bit Serial I/O SMR (serial mode register) Address bit7 0039 SIOF SDR (serial data register) Address bit7 003A R/W : Readable and Writable : Undefined Note: When using a bit manipulation instruction, make sure that the SST bit is "0".
Page 336: Serial Mode Register (Smr)
CHAPTER 14 8-BIT SERIAL I/O 14.4.1 Serial Mode Register (SMR) The serial mode register (SMR) is used to allow and prohibit 8-bit serial I/O operation, select a shift clock, set a transfer direction, control interrupts, and check interrupt states. ■ Serial Mode Register (SMR) Address bit7...
Page 337 Table 14.4-1 Explanation of Functions of Each Bit in Serial Mode Register (SMR) (1/2) Bit name SIOF: bit7 Interrupt request flag bit SIOE: bit6 Interrupt request allowance bit SCKE: bit5 Shift clock output allowance bit SOE: bit4 Serial data output allowance bit bit3, CKS1, CKS0:...
Page 338 CHAPTER 14 8-BIT SERIAL I/O Table 14.4-1 Explanation of Functions of Each Bit in Serial Mode Register (SMR) (2/2) Bit name BDS: bit1 Transfer direction selection bit SST: bit0 Serial I/O transfer start bit Function This bit is used to select whether to transfer serial data, starting at the lowest bit (LSB first, BDS = 0) or the highest bit (MSB first, BDS = 1).
Page 339: Serial Data Register (Sdr)
14.4.2 Serial Data Register (SDR) The serial data register (SDR) retains 8-bit serial I/O transfer data. The SDR functions as a transmission data register at serial output operation. It functions as a reception data register at serial input operation. ■ Serial Data Register (SDR) Figure 14.4-3 shows the bit structure of the SDR.
Page 340: Interrupt Of 8-Bit Serial I/O
CHAPTER 14 8-BIT SERIAL I/O 14.5 Interrupt of 8-Bit Serial I/O An 8-bit serial I/O interrupt is caused by completion of 8-bit serial data I/O. ■ Interrupt at Serial I/O Operation In the 8-bit serial I/O, serial output operation and serial input operation are performed at the same time. When serial I/O transfer is started, the values in the serial data register (SDR) are input and output on a per bit basis in synchronization with the set shift clock cycle.
Page 341: Operations Of Serial Output Functions
14.6 Operations of Serial Output Functions In the 8-bit serial I/O, 8-bit serial output operation synchronized with a shift clock is possible. ■ Serial Output Operation Serial output operation is divided into serial output operation using an internal shift clock and serial output operation by using the external shift clock.
Page 342: Operation At Serial Output Completion
CHAPTER 14 8-BIT SERIAL I/O ● Serial output operation using external shift clock Serial output operation with the external shift clock requires the settings shown in Figure 14.6-2 . Figure 14.6-2 Settings Required for Serial Output Operation using External Shift Clock DDR3 SSEL : Used bit...
Page 343: Operations Of Serial Input Functions
14.7 Operations of Serial Input Functions In the 8-bit serial I/O, 8-bit serial input operation synchronized with a shift clock is possible. ■ Serial Input Operation Serial input operation is divided into serial input operation with an internal shift clock and serial input operation with an external shift clock.
Page 344: Operation At Serial Input Completion
CHAPTER 14 8-BIT SERIAL I/O ● Serial input operation using external shift clock Serial input operation with the external shift clock requires the settings shown in Figure 14.7-2 . Figure 14.7-2 Settings Required for Serial Input Operation using External Shift Clock DDR3 SSEL : Used bit...
Page 345: 8-Bit Serial I/O Operation In Each Mode
14.8 8-Bit Serial I/O Operation in Each Mode This section describes the operation of the 8-bit serial I/O if the 8-bit serial I/O switches to sleep or stop mode or a stop request is issued when it is in operation. ■...
Page 346 CHAPTER 14 8-BIT SERIAL I/O Figure 14.8-2 8-bit Serial I/O Operation in Stop Mode (Internal Shift Clock) SCK output SST bit SIOF bit SO pin output STP bit (STBC register) ● 8-bit serial I/O operation at issuance of stop request during operation As shown in Figure 14.8-3 , if operation is stopped (SMR: SST = 0) during data transfer, the 8-bit serial I/O stops data transfer and clears the shift clock counter.
Page 347: When The External Shift Clock Is Used
■ When the External Shift Clock is Used ● 8-bit serial I/O operation in sleep mode In sleep mode, as shown in Figure 14.8-4 , the 8-bit serial I/O continues data transfer without stopping the serial I/O operation. Figure 14.8-4 8-bit Serial I/O Operation in Sleep Mode (External Shift Clock) SCK input SST bit SIOF bit...
Page 348 CHAPTER 14 8-BIT SERIAL I/O ● 8-bit serial I/O operation at issuance of stop request during operation As shown in Figure 14.8-6 , if operation is stopped (SMR: SST = 0) during data transfer, the 8-bit serial I/O stops data transfer and clears the shift clock counter. For this reason, the transfer destination must also be initialized.
Page 349: Notes On Using 8-Bit Serial I/O
14.9 Notes on Using 8-Bit Serial I/O This section provides notes on using the 8-bit serial I/O. ■ Notes on Using 8-bit Serial I/O ● Error at serial transfer start The time at which serial I/O transfer is started with a serial transfer program (SMR: SST = 1) is asynchronous with the time when the falling edge (output) or rising (input) edge of a shift clock occurs.
Page 350: 14.10 Example Of 8-Bit Serial I/O Connection
CHAPTER 14 8-BIT SERIAL I/O 14.10 Example of 8-Bit Serial I/O Connection This section provides an example of mutual connection between 8-bit serial I/Os of MB89202/F202RA series for bidirectional serial I/O operation. ■ When Bidirectional Serial I/O Operation is Performed Figure 14.10-1 Example of 8-bit Serial I/O Connection (Interface between MB89202/F202RA Series) SIO-A SIO-B...
Page 351 Figure 14.10-2 Bidirectional Serial I/O Operation SIO-A START Stop SIO-A operation (SST=0) Set SI pin to serial data input (input port) Set SCK pin to shift clock output - Set SO pin to serial data output - Select internal shift clock Set data transfer (shift clock) direction Is SIO-B in...
Page 352: 14.11 Program Example For 8-Bit Serial I/O
CHAPTER 14 8-BIT SERIAL I/O 14.11 Program Example for 8-Bit Serial I/O This section provides program example for 8-bit serial I/O. ■ Program Example for 8-bit Serial Output ● Processing Specifications • The 8-bit serial output program outputs 8-bit serial data (55 When serial I/O transfer terminates, an interrupt occurs.
Page 353: Program Example For 8-Bit Serial Input
;--------------------Interrupt processing routine---------------------------------------------------------- WARI CLRB PUSHW XCHW PUSHW SETB User processing POPW XCHW POPW RETI ENDS ; ------------------------------------------------------------------------------------------------------------------- ■ Program Example for 8-bit Serial Input ● Processing specifications • The 8-bit serial input program inputs 8-bit serial data from the SI pin of the 8-bit serial I/O. When serial I/O transfer terminates, an interrupt occurs.
Page 354 CHAPTER 14 8-BIT SERIAL I/O SETB SETI ;--------------------Interrupt processing routine----------------------------------------------------------- WARI CLRB PUSHW XCHW PUSHW SETB User processing POPW XCHW POPW RETI ENDS ; -------------------------------------------------------------------------------------------------------------------- SMR,#01001100B ; Clears the interrupt request flag, allows the interrupt request output, sets shift clock input (SCK), prohibits serial data output (SO), selects the external shift clock, and sets LSB first.
Page 355: Chapter 15 Buzzer Output
CHAPTER 15 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output. 15.1 Overview of the Buzzer Output 15.2 Configuration of the Buzzer Output 15.3 Pin of the Buzzer Output 15.4 Buzzer Register (BZCR) 15.5 Program Example for Buzzer Output...
Page 356: Overview Of The Buzzer Output
CHAPTER 15 BUZZER OUTPUT 15.1 Overview of the Buzzer Output For the buzzer output, four kinds of output frequencies (square waves) can be selected. The buzzer output may be used for the confirmation tone of key input and other tones. ■...
Page 357: Configuration Of The Buzzer Output
15.2 Configuration of the Buzzer Output The buzzer output consists of the following two blocks: • Buzzer output selector • Buzzer register (BZCR) ■ Block Diagram of the Buzzer Output Figure 15.2-1 Block Diagram of Buzzer Output BZCR From time-base timer : Oscillation frequency ●...
Page 358: Pin Of The Buzzer Output
CHAPTER 15 BUZZER OUTPUT 15.3 Pin of the Buzzer Output The pin related to the buzzer output is P37/BZ/PPG. ■ P37/BZ/PPG Pin The P37/BZ/PPG pin works as a general-purpose I/O (P37) pin, output pin for the buzzer output (BZ), or output pin for the 12-bit PPG (PPG).
Page 359: Buzzer Register (Bzcr)
15.4 Buzzer Register (BZCR) The buzzer register (BZCR) is used to select an output frequency of the buzzer and also serves as the buzzer output enable. ■ Buzzer Register (BZCR) Address bit7 bit6 bit5 0018 : Readable/Writable : Unused : Initial value : Oscillation frequency Figure 15.4-1 Buzzer Register (BZCR) bit4...
Page 360 CHAPTER 15 BUZZER OUTPUT Table 15.4-1 Functions of Each Bit in Buzzer Register (BZCR) Bit name bit7 bit3 bit2 bit0 • Undefined at read Unused bits • No effect on the operation at write • Select a buzzer output and enable the output. •...
Page 361: Program Example For Buzzer Output
15.5 Program Example for Buzzer Output This section shows an program example for buzzer output. ■ Program Example for Buzzer Output ● Processing specification Suppose that the buzzer output of 3.052 kHz is output to the BZ pin and then the buzzer output is cut off. If 2 is selected when the oscillation (F follows:...
Page 362 CHAPTER 15 BUZZER OUTPUT...
Page 363: Chapter 16 Wild Register Function
CHAPTER 16 WILD REGISTER FUNCTION This chapter describes the functions and operation of the wild registers. 16.1 Overview of the Wild Register Function 16.2 Configuration of the Wild Register Function 16.3 Registers of the Wild Register Function 16.4 Operations of the Wild Register Functions...
Page 364: Overview Of The Wild Register Function
CHAPTER 16 WILD REGISTER FUNCTION 16.1 Overview of the Wild Register Function The wild register function is a function for patching the faulty part of a program by setting the address and the correct data in the incorporated registers. Up to two bytes of data correction is possible.
Page 365: Configuration Of The Wild Register Function
16.2 Configuration of the Wild Register Function The wild register function consists of the following two blocks: Memory area part • Data setting register (WRDR) • Higher address set register (WRARH) • Lower address set register (WRARL) Control circuit part ■...
Page 366: Registers Of The Wild Register Function
CHAPTER 16 WILD REGISTER FUNCTION 16.3 Registers of the Wild Register Function Figure 16.3-1 shows the registers related to the wild register function. ■ Registers Related to the Wild Register Function Figure 16.3-1 Registers Related to Wild Register Function (Data setting register) WRDR0,WRDR1 Address bit7...
Page 367: Data Setting Registers (Wrdr0 And Wrdr1)
16.3.1 Data Setting Registers (WRDR0 and WRDR1) The data setting registers (WRDR0 and WRDR1) are registers where the correct data used by the wild register function is set. ■ Data Setting Register (WRDR) bit7 Address WRDR0 0042 RD07 WRDR1 0045 RD07 R/W : Readable and Writable : Undefined...
Page 368: Higher Address Set Registers (Wrarh0 And Wrarh1)
CHAPTER 16 WILD REGISTER FUNCTION 16.3.2 Higher Address Set Registers (WRARH0 and WRARH1) The higher address set registers (WRARH0 and WRARH1) are registers where the higher byte of addresses to be corrected by the wild register function are set. ■ Higher Address Set Register (WRARH) Figure 16.3-3 Higher Address Set Register (WRARH) Address...
Page 369: Lower Address Set Registers (Wrarl0 And Wrarl1)
16.3.3 Lower Address Set Registers (WRARL0 and WRARL1) The lower address set registers (WRARL0 and WRARL1) are registers where the lower byte of addresses to be corrected by the wild register function are set. ■ Lower Address Set Register (WRARL) Figure 16.3-4 Lower Address Set Register (WRARL) Address bit7...
Page 370: Address Comparison En Register (Wren)
CHAPTER 16 WILD REGISTER FUNCTION 16.3.4 Address Comparison EN Register (WREN) The address comparison EN register (WREN) is a register that enables the operation of wild register function for the individual wild register numbers. ■ Address Comparison EN Register (WREN) Figure 16.3-5 Address Comparison EN Register (WREN) bit7 Address...
Page 371: Data Test Set Register (Wror)
CHAPTER 16 WILD REGISTER FUNCTION 16.3.5 Data Test Set Register (WROR) A test register. Do not access this register.
Page 372: Operations Of The Wild Register Functions
CHAPTER 16 WILD REGISTER FUNCTION 16.4 Operations of the Wild Register Functions This section describes the operation order of the wild register. ■ Operation Order of the Wild Register Function Table 16.4-1 describes the operation order of the wild register. In the operation example column, it corrects data at address FC36 Table 16.4-1 Operation Order of Wild Register Set an address of the wild register correspondence area to...
Page 373: Chapter 17 Flash Memory
CHAPTER 17 FLASH MEMORY This chapter describes the functions and operation of the 128K-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: 1. Parallel programmer 2. Writing/erasing data using a serial programmer 3.
Page 374: Overview Of Flash Memory
CHAPTER 17 FLASH MEMORY 17.1 Overview of Flash Memory The 128K-bit flash memory is mapped to the C000 map. The functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory.
Page 375: Flash Memory Control Status Register (Fmcs)
17.2 Flash Memory Control Status Register (FMCS) The flash memory control status register (FMCS), together with the flash memory interface circuit, is used to write data to and erase data from the flash memory. ■ Flash Memory Control Status Register (FMCS) Figure 17.2-1 Flash Memory Control Status Register (FMCS) Address bit7...
Page 376 CHAPTER 17 FLASH MEMORY Table 17.2-1 Explanation of Functions of Each Bit in the Flash Memory Control Status Register (FMCS) Bit name INTE: Bit causing an interrupt (IRQB) to the CPU to be generated when writing into or erasing Causing an from flash memory is completed.
Page 377: Starting The Flash Memory Automatic Algorithm
17.3 Starting the Flash Memory Automatic Algorithm Four types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. ■ Command Sequence Table Table 17.3-1 lists the commands used for flash memory write/erase. Table 17.3-1 Command Sequence Table Command 1st bus write sequence...
Page 378: Confirming The Automatic Algorithm Execution State
CHAPTER 17 FLASH MEMORY 17.4 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequence flags.
Page 379: Data Polling Flag (Dq7)
17.4.1 Data Polling Flag (DQ7) The data polling flag uses the data polling function to post that the automatic algorithm is being executed or has terminated ■ Write Read-access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit7 last written, regardless of the value at the address specified by the address signal.
Page 380: Toggle Bit Flag (Dq6)
CHAPTER 17 FLASH MEMORY 17.4.2 Toggle Bit Flag (DQ6) Like the data polling flag, the toggle bit flag uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. ■ Automatic Write/Erase Making successive read accesses while the automatic writing/erasing algorithm is being performed toggles flash memory and makes it output 1 and then 0, in turn, regardless of the specified address.
Page 381: Timing Limit Exceeded Flag (Dq5)
17.4.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. ■ Automatic Write/Erase Bit5 indicates that execution of the automatic algorithm exceeded the time (internal pulse count) specified in flash memory.
Page 382: Toggle Bit-2 Flag (Dq2)
CHAPTER 17 FLASH MEMORY 17.4.4 Toggle Bit-2 Flag (DQ2) The toggle bit-2 flag (DQ2) is used to detect that flash memory is performing an automatic erase operation, together with the toggle bit. ■ Automatic Write/Erase Making successive read accesses while the automatic erasing algorithm is being performed toggles flash memory and makes it output 1 and then 0, in turn, regardless of the specified address.
Page 383: Detailed Explanation Of Writing To Erasing Flash Memory
17.5 Detailed Explanation of Writing to Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase, when a command that starts the automatic algorithm is issued. ■ Detailed Explanation of Flash Memory Write/Erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 17.3-1 in Section "17.3 Starting the Flash Memory Automatic Algorithm "for a write cycle to the bus to perform Read/Reset, Write, Chip Erase operations.
Page 384: Setting The Read/Reset State
CHAPTER 17 FLASH MEMORY 17.5.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. ■ Setting the Read/Reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 17.3-1 in Section "17.3 Starting the Flash Memory Automatic Algorithm ") continuously to the target sector in the flash memory.
Page 385: Writing Data
17.5.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. Figure 17.5-1 shows an example of the flash memory write procedure. ■ Writing Data The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 17.3-1 in Section "17.3 Starting the Flash Memory Automatic Algorithm ") continuously to the flash memory.
Page 386 CHAPTER 17 FLASH MEMORY Figure 17.5-1 Example of the Flash Memory Write Procedure Write error Start writing* FMCS: WE (bit5) Enable flash memory write Write command sequence (1) FAAA <-- AA (2) F554 <-- 55 (3) FAAA <-- A0 (4) Write address <-- Write data Read internal address Data Data polling (DQ7)
Page 387: Erasing All Data (Erasing Chips)
17.5.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. ■ Erasing All Data (Erasing Chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 17.3-1 in Section "17.3 Starting the Flash Memory Automatic Algorithm ") continuously to the target sector in the flash memory.
Page 388: Flash Security Feature
CHAPTER 17 FLASH MEMORY 17.6 Flash Security Feature Flash security feature provides possibilities to protect the content of the flash memory from being read from external. ■ Abstract By writing the protection code of "01 access to the flash memory is restricted. Once the flash memory is protected, unlock the security function can only be done by performing the chip erase operation.
Page 389: Notes On Using Flash Memory
17.7 Notes on using Flash Memory This section provides notes on using the MB89F202, especially for flash memory. ■ Input of a Hardware Reset (RST) To input a hardware reset when reading is in progress, i.e., when the automatic algorithm has not been started, secure a minimum low-level width of 1650 ns.
Page 390 CHAPTER 17 FLASH MEMORY...
Page 391: Appendix
APPENDIX This appendix shows the I/O map, the overview of the instructions, mask options in MB89202/F202RA series, and the pin states. APPENDIX A I/O Map APPENDIX B Overview of the Instructions APPENDIX C Mask Options APPENDIX D Programming EPROM with Evaluation Chip APPENDIX E Pin State of the MB89202/F202RA Series...
Page 392: Appendix A I/O Map
APPENDIX A I/O Map APPENDIX A I/O Map For the registers of peripheral functions incorporated in the MB89202/F202RA series, the addresses shown in Table A-1 are assigned. ■ I/O Map Table A-1 I/O Map (1 / 4) Register Address abbreviation 0000 PDR0 0001...
Page 393 Table A-1 I/O Map (2 / 4) Register Address abbreviation 0018 BZCR 0019 TCCR 001A TCR1 001B TCR0 001C TDR1 001D TDR0 001E TCPH 001F TCPL 0020 TCR2 0021 0022 CNTR 0023 COMR 0024 EIC1 0025 EIC2 0026 0027 0028 0029 002A SIDR...
Page 394 APPENDIX A I/O Map Table A-1 I/O Map (3 / 4) Register Address abbreviation 0034 ADEN 0035 0036 EIE2 0037 EIF2 0038 0039 003A 003B SSEL 003C 003F 0040 WRARH0 0041 WRARL0 0042 WRDR0 0043 WRARH1 0044 WRARL1 0045 WRDR1 0046 WREN 0047...
Page 395 Table A-1 I/O Map (4 / 4) Register Address abbreviation 0066 006F 0070 PUL0 0071 PUL3 0072 PUL5 0073 0078 0079 FMCS 007A 007B ILR1 007C ILR2 007D ILR3 007E ILR4 007F ● Explanation on read/write R/W: Readable and Writable R: Read only W: Write only ●...
Page 396: Appendix B Overview Of The Instructions
APPENDIX B Overview of the Instructions APPENDIX B Overview of the Instructions This section describes the instructions used for the F ■ Overview of the Instructions of the F The F MC-8L has 140 kinds of 1-byte machine instructions (actually, the map is 256 bytes). An instruction and succeeding operands make an instruction code.
Page 397 ■ Explanation on the Codes Representing Instructions Table B-1 describes the codes used to explain the instruction codes in Appendix B. Table B-1 Explanation on Codes on Instructions’ List Code #vct #d16 dir:b ((X)) Meaning Direct address (8 bits) Offset (8 bits) Extended address (16 bits) Vector table number (3 bits) Immediate data (8 bits)
Page 398 APPENDIX B Overview of the Instructions ■ Explanation on the Items of Instructions’ List Table B-2 Explanation on Items of Instructions’ List Item MNEMONIC Operation TL,TH,AH N,Z,V,C OP CODE Represents the instruction coded in the assembler. Indicates the number of cycles of the instruction (number of instruction cycles). Indicates the number of bytes of the instruction.
Page 399: Addressing
Addressing For the F MC-8L, the following 10 kinds of addressing modes are supported: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing • Vector addressing •...
Page 400 APPENDIX B Overview of the Instructions ● Bit Direct Addressing The addressing, which is indicated by dir:b in the instructions list, is used for accessing the area from 0000 to 00FF on a per bit basis. In this addressing, the higher one byte of the address is 00 lower one byte with the operand;...
Page 401 ● General-purpose Register Addressing The addressing, which is indicated by Ri in the instructions list, is used for accessing the register bank of the general-purpose register area. In this addressing, the higher one byte of the address is fixed to 01. The lower one byte is generated from the contents of RP (register bank pointer) and the lower three bits of the operation code.
Page 402 APPENDIX B Overview of the Instructions Figure B.1-8 shows an example. CALL V #5 ● Relative Addressing The addressing, which is indicated by rel in the instructions list, is used for branching to the area of 128 bytes before or after the PC (program counter). In this addressing, the contents of the operand with a sign are added to the PC.
Page 403: Special Instructions
Special Instructions This section describes the special instructions other than addressing. ■ Special Instructions ● JMP @A By this instruction, the control branches to PC (program counter) using the contents of A (accumulator) as the address. N items of jump destinations have been listed on the table, one of which is selected and transferred to A.
Page 404 APPENDIX B Overview of the Instructions ● MULU A This instruction multiplies AL (the lower eight bits of accumulator) by TL (the lower eight bits of the temporary accumulator) without a sign and stores the results in 16 bits length to A. The contents of T (temporary accumulator) remain as they are.
Page 405 ● XCHW A, PC This instruction replaces the contents of A and the contents of PC, resulting in a branch to the address indicated by the contents of A before execution. The contents of A after execution become the value of the address next to the address holding the operation code, XCHW A, PC.
Page 406 APPENDIX B Overview of the Instructions ● CALLV #vct This addressing is used for branching to one of the subroutine addresses registered in the table. After the return address (the contents of PC) is saved to the address indexed by SP (stack pointer), the control is branched to the address listed in the vector table via the vector addressing.
Page 407: Bit Manipulation Instructions (Setb And Clrb)
Bit Manipulation Instructions (SETB and CLRB) Some registers of peripheral functions have bits that perform a read operation different from ordinary read for a bit manipulation instruction. ■ Read-modify-write Operation The bit manipulation instructions can set "1" (SETB) to the specified bit in a register or RAM or clear it to "0"...
Page 408: F 2 Mc-8L Instructions List
APPENDIX B Overview of the Instructions MC-8L Instructions List Table B.4-1 to Table B.4-4 list the instructions used by the F ■ Transfer Instructions Table B.4-1 List of Transfer Instructions (1 / 2) MNEMONIC MOV dir, A MOV @IX+off, A MOV ext, A MOV @EP, A MOV Ri, A...
Page 409 Table B.4-1 List of Transfer Instructions (2 / 2) MNEMONIC MOVW A, dir MOVW A, @IX+off MOVW A, ext MOVW A, @A MOVW A, @EP MOVW A, EP MOVW EP, #d16 MOVW IX, A MOVW A, IX MOVW SP, A MOVW A, SP MOV @A, T MOVW @A, T...
Page 410: Operation Instructions
APPENDIX B Overview of the Instructions Note: At byte transfer operation to A, the automatic transfer to T is represented by TL ← AL. The operands in a multiple-operand instruction are stored in the order in which they are indicated in MNEMONIC.
Page 411 Table B.4-2 List of Operation Instructions (2 / 4) MNEMONIC ANDW A ORW A XORW A CMP A CMPW A RORC A ROLC A CMP A, #d8 CMP A, dir CMP A, @EP CMP A, @IX+off CMP A, Ri XOR A XOR A, #d8 XOR A, dir XOR A, @EP...
Page 412 APPENDIX B Overview of the Instructions Table B.4-2 List of Operation Instructions (3 / 4) MNEMONIC XOR A, @IX+off XOR A, Ri AND A AND A, #d8 AND A, dir AND A, @EP AND A, @IX+off AND A, Ri OR A OR A, #d8 OR A, dir OR A, @EP...
Page 413: Branch Instructions
Table B.4-2 List of Operation Instructions (4 / 4) MNEMONIC CMP @EP, #d8 CMP @IX+off, #d8 CMP Ri, #d8 INCW SP DECW SP ■ Branch Instructions Table B.4-3 List of Branch Instructions MNEMONIC BZ/BEQ rel BNZ/BNE rel BC/BLO rel BNC/BHS rel BN rel BP rel BLT rel...
Page 414: Other Instructions
APPENDIX B Overview of the Instructions ■ Other Instructions Table B.4-4 List of Other Instructions MNEMONIC PUSHW A POPW A PUSHW IX POPW IX CLRC SETC CLRI SETI Operation ( (SP) ) ← (A), (SP) ← (SP)-2 (A) ← ((SP)), (SP) ← (SP)+2 ( (SP) ) ←...
Page 415: Instruction Map
Instruction Map Table B.5-1 shows the instruction map of the F MC-8L. ■ Instruction Map Table B.5-1 Instruction Map of the F MC-8L...
Page 416: Appendix C Mask Options
APPENDIX C Mask Options APPENDIX C Mask Options Table C-1 lists the mask options of the MB89202/F202RA series. ■ Mask Options Table C-1 Mask Options Part number Specifying procedure Selection of initial value of main clock oscillation settling time* (with F = 12.5 MHz) 01 : 2 (Approx.1.31 ms)
Page 417: Appendix D Programming Eprom With Evaluation Chip
APPENDIX D Programming EPROM with Evaluation Chip This section describes how to program EPROM with evaluation chip. ■ Programming EPROM with Evaluation Chip ● EPROM for use 32 Kbyte EPROM (equivalent to MBM27C256A DIP-28) Figure D-1 Memory Map of the Evaluation Chip 0000 0080 0280...
Page 418: Appendix E Pin State Of The Mb89202/F202Ra Series
APPENDIX E Pin State of the MB89202/F202RA Series APPENDIX E Pin State of the MB89202/F202RA Series Table E-1 describes the pin states in each operation mode of the MB89202/F202RA series. ■ Pin States in Each Operation Mode Table E-1 Pin States in Each Operation Mode In normal operation Pin name mode...
Page 419: Index
INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 420 INDEX Index Numerics 12-bit PPG 12-bit PPG Function ... 207 12-bit PPG Control Register 12-bit PPG Control Register 1 (RCR21) ... 214 12-bit PPG Control Register 2 (RCR22) ... 215 12-bit PPG Control Register 3 (RCR23) ... 216 12-bit PPG Control Register 4 (RCR24) ... 218 12-bit PPG Timer Block Diagram of 12-bit PPG Timer ...
Page 421 A/D Control Register A/D Control Register 1 (ADC1) ... 266 A/D Control Register 2 (ADC2) ... 268 A/D Conversion A/D Conversion Functions... 260 Interrupt when A/D Conversion Functions are Enabled ... 272 Operations of A/D Conversion Functions ... 274 Program Example of the A/D Conversion Functions ...
Page 422 INDEX Block Diagram of the Wild Register Function ... 349 Block Diagram of Time-base Timer ... 118 Block Diagram of UART ... 284 Block Diagram of Watchdog Timer ... 129 Branch Branch Instructions... 397 Buzzer Output Block Diagram of the Buzzer Output... 341 Block Diagram of the Pin Related to the Buzzer Output ...
Page 423 Command Sequence Command Sequence Table... 361 COMR PWM Compare Register (COMR) ... 145 Condition Code Register Configuration of the Condition Code Register (CCR) ... 29 Configuration Configuration of Memory Space... 22 Configuration of the Condition Code Register (CCR) ... 29 Configuration of the General-purpose Registers ...
Page 424 INDEX Functions of External Interrupt Circuit 2 (Level Detection) ... 244 Interrupt during the Operation of External Interrupt Circuit 1 ... 237 Interrupt during the Operation of External Interrupt Circuit 2 ... 253 Operation of External Interrupt Circuit 1 ... 239 Operation of External Interrupt Circuit 2 ...
Page 425 High voltage High voltage supply on RST pin (applicable to MB89F202RA only) ... 358 Higher Address Set Register Higher Address Set Register (WRARH)... 352 How to How to disable the Flash Security Feature ... 372 How to enable the Flash Security Feature ... 372 8-bit Serial I/O Interrupt Register and Vector Table ...
Page 426 INDEX Program Example for External Interrupt Circuit 2 ... 256 Reception Interrupt... 303 Register and Vector Table Related to 8/16-bit Capture Timer/Counter of Interrupts... 184 Register and Vector Table Related to Interrupts from Time-base Timer ... 121 Register and Vector Table Related to the Interrupt of the A/D Converter ...
Page 427 Multiple Interrupts Multiple Interrupts ... 39 Notes Notes on Setting Standby Mode... 70 Notes on Using 12-bit PPG Timer ... 221 Notes on Using 8-bit PWM Timer ... 155 Notes on Using 8-bit Serial I/O ... 333 Notes on Using the 8/16-bit Capture Timer/Counter ...
Page 428 INDEX P37/BZ/PPG P37/BZ/PPG Pin ... 342 Package Dimension Package Dimension of DIP-32P-M06... 10 Package Dimension of FPT-34P-M03 ... 11 Registers of Port 4 ... 91 Registers of Port 5 ... 95 Registers PDR0, DDR0, and PUL0 of Port 0... 79 Registers PDR3, DDR3, and PUL3 of Port 3...
Page 429 Programming EPROM Programming EPROM with Evaluation Chip ... 401 Programming Example External Interrupt Circuit 1 Programming Example ... 241 Programming Examples for Time-base Timer ... 125 Programming Examples of Watchdog Timer ... 133 Registers of Port 5... 95 Registers PDR0, DDR0, and PUL0 of Port 0 ... 79 Registers PDR3, DDR3, and PUL3 of Port 3 ...
Page 430 INDEX Register and Vector Table Related to 8/16-bit Capture Timer/Counter of Interrupts... 184 Register and Vector Table Related to Interrupts from Time-base Timer ... 121 Register and Vector Table Related to the Interrupt of the A/D Converter ... 272 Register and Vector Table Related to the Interrupts of an 8-bit PWM Timer...
Page 431 When Bidirectional Serial I/O Operation is Performed ... 334 Serial Input Operation at Serial Input Completion ... 328 Program Example for 8-bit Serial Input ... 337 Serial Input Operation ... 327 Serial Input Data Register Serial Input Data Register (SIDR)... 297 Serial Mode Control Register Serial Mode Control Register (SMC) ...
Page 432 INDEX TBTC Time-base Timer Control Register (TBTC)... 119 TCCR Capture Control Register (TCCR) ... 171 TCPH and TCPL Capture Data Registers H and L (TCPH and TCPL) ... 182 Timer 0 Control Register (TCR0) ... 173 Timer 1 Control Register (TCR1) ... 175 Timer Output Control Register (TCR2) ...
Page 433 Operations of Watchdog Timer ... 131 Programming Examples of Watchdog Timer ... 133 Software Reset,Watchdog Timer Reset ... 373 Watchdog Timer Function ... 128 WDTC Watchdog Control Register (WDTC) ... 130 Wild Register Block Diagram of the Wild Register Function ...
Page 434 INDEX...
Page 435 FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL MC-8L 8-BIT MICROCONTROLLER MB89202/F202RA Series HARDWARE MANUAL FUJITSU LIMITED Published Strategic Business Development Dept. Edited CM25-10153-2E February 2008 the second edition Electronic Devices...

This manual is also suitable for:

F2mc-8l mb89202 Mb89202/f202ra series

Fujitsu F2MC-8L F202RA Hardware Manual

Chapter 1 Overview

Chapter 2 Handling Devices

Chapter 3 Cpu

Chapter 4 I/O Ports

Chapter 5 Time-Base Timer

Chapter 6 Watchdog Timer

Chapter 7 8-Bit Pwm Timer

Chapter 8 8/16-Bit Capture Timer/Counter

Chapter 9 12-Bit Ppg Timer

Chapter 10 External Interrupt Circuit 1 (Edge)

Chapter 11 External Interrupt Circuit 2 (Level)

Chapter 12 A/D Converter

Chapter 13 Uart

Chapter 14 8-Bit Serial I/O

Chapter 15 Buzzer Output

Chapter 16 Wild Register Function

Chapter 17 Flash Memory

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